EDA程序设计试题及答案(共24页)

1、精选优质文档-倾情为你奉上1 请画出下段程序的真值表，并说明该电路的功能。LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY aaa IS PORT( oe,dir :IN STD_LOGIC ; a,b : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0 ) ; END aaa ;ARCHITECTURE ar OF aaa ISBEGIN PROCESS(oe , dir ) 输入 输出 BEGIN a1 a0 x3 x2 x1 x0 IF oe=0 THEN a<=”zzzzzzzz”; b<=”zzzzzzzz

2、”; 0 0 0 0 0 1 ELSIF oe=1 THEN 0 1 0 0 1 0 IF dir=0 THEN b<=a; 1 0 0 1 0 0 ELSIF dir=1 THEN a<=b; 1 1 1 0 0 0 ENDIF; END IF ; END PROCESS ;END ar ;功能为：24译码器.4分2 请说明下段程序的功能，写出真值表，并画出输入输出波形。LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;ENTI

3、TY aaa IS PORT( reset,clk: IN STD_LOGIC; q: BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0);END aaa;ARCHITECTURE bd OF aaa IS BEGIN PROCESS(clk,reset) BEGIN IF (reset='0') THEN q<="000" ELSIF (clk'event AND clk='1') THEN IF (q=5) THEN q<="000" ELSE q<=q+1; END IF

4、; END IF; END PROCESS;END bd;功能为：带进位借位的4位加/减法器。.3分输入输出波形图如下：7分ma3.0b3.0c3.0d1.试用VHDL语言编程实现74LS273芯片的功能。LIBRARY ieee; USEieee.std_logic_1164.ALL;2ENTITYls273IS1PORT(clr,clk:INstd_logic; d:INstd_logic_vector(7DOWNTO 0 );q:OUTstd_logic_vector(7 DOWNTO 0 );4);ENDls273; ARCHITECTURElock8OFls273IS1BEGINPR

5、OCESS ( clk )1BEGINIF (CLR=0)THENq<=” ;2 ELSEIF (clkevent AND clk=1) THEN q<=d; 3ELSEIF ( clk=0 ) THEN q<=q; 1END IF;ENDPROCESS;ENDlock8;3. 请用VHDL语言编程实现一个状态向量发生器。LIBRARY ieee; USEieee.std_logic_1164.ALL;2ENTITYstasIS1PORT(cp, rst:INstd_logic; p:BUFFERstd_logic_vector(7 DOWNTO 0 );2);ENDstas

6、; ARCHITECTUREarstasOFstasIS1BEGINPROCESS (cp )1BEGINIF(rst=”0”) THENp<=”;1ELSEIF (cpevent AND cp=1 )1WITHpSELECTp<=”WHEN“”;”WHEN“”;”WHEN“”;”WHEN“”;”WHEN“”;”WHEN“”;”WHENOTHERS; 6END IFENDPROCESS;ENDarstas;1. 阅读下段程序，画出该电路的真值表，并详细说明该电路的功能。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOG

7、IC_UNSIGNED.ALL;ENTITY ab_8 IS PORT( a, b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); ahb, alb, aeb: OUT STD_LOGIC);END ab_8;ARCHITECTURE bd OF ab_8 IS BEGIN PROCESS(a,b) BEGIN IF a>b THEN ahb<=1; alb<=0; aeb<=0; ELSIF a<b THEN ahb<=0; alb<=1; aeb<=0; ELSE ahb<=0; alb<=0; aeb<

8、;=1; END IF; END PROCESS;END bd;1.（1）真值表如下：(5)输 入输 出a、bahbalbaeba>b100a<b010a=b001（2）该电路是一个8位两输入比较器，（2）a、b是两个8位输入端；（1）ahb、alb和aeb为比较结果输出端，某种比较结果为真时，相应的输出端为“1”，其余端输出为“0”。（2）1. 试用VHDL语言编程实现一个2-4译码器，其真表如下：输入端输出端enselecty0XX“1111”100“1110”101“1101”110“1011”111“0111” 2-4译码器码参考程序如下：（答案不唯一，用case语句、wi

9、thselect语句都可以。）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;(1)ENTITY ym24 IS PORT( en : IN STD_LOGIC; select : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)(3);END ym24;ARCHITECTURE bd OF ym24 IS BEGIN PROCESS(en)(1) IF (en=1) THEN y<= ”1110” WHEN select=”00” ELSE ”1101” WHE

10、N select =”01” ELSE ”1011” WHEN select =”10” ELSE ”0111” WHEN select =”11” ELSE(4) ”1111”; ELSE y<=”1111”; END PROCESS;END bd;2. 试用VHDL语言设计一个六路8位总线复用器，其中A、B、C、D、E、F都是8位输入总线，Q为8位输出总线，S为3位选择端，其功能如下： 输入端输出端S2S1S0Q7Q0000Q=A001Q=B010Q=C011Q=D100Q=E101Q=F其它B=“” 六路8位总线复用器参考程序：（答案不唯一）LIBRARY ieee;USE iee

11、e.std_logic_1164.ALL;ENTITY mux6 IS(1)PORT( S : IN std_logic_vector(2 DOWNTO 0); A,B,C,D,E,F: IN std_logic_vector(7 DOWNTO 0); Q: OUT std_logic_vector(7 DOWNTO 0) );(3)END mux6;ARCHITECTURE bd OF mux6 ISBEGIN PROCESS(S) BEGIN(1) CASE S IS WHEN "000"=>Q<=A; WHEN "001"=>Q&

12、lt;=B; WHEN "010"=>Q<=C; WHEN "011"=>Q<=D; WHEN "100"=>Q<=E; WHEN "101"=>Q<=F; WHEN OTHERS=>Q<=""(4) END CASE; END PROCESS;END bd;2、已知三选一电路如图，判断下列程序是否有错误，如有则指出错误所在，并给出完整程序。（10分）library ieee;use ieee.std_logic_1164.all;EN

13、TITY MAX isport(a1,a2,a3,s0,s1:in bit; outy:out bit);end max; （2）architecture one of max iscomponent mux21a port(a,b,s:in std_logic; y:out std_logic);end component; （2）signal temp std_logic; （2）begin u1:mux21a port map(a2,a3,s0,temp); （2） u2:mux21a port map(a1,temp,s1,outy); （2） end one;1. 已知电路原理图如下

14、，请用VHDL语言编写其程序答：library ieee;use ieee.std_logic_1164.all;entity mux21 is port(a,b,s:in bit; y:out bit);end mux21; （4）architecture one of mux21 is single d,e:bit;begin d<=a and (not)s; e<=b and s; y<=d or e;end one; 2. 设计一个带有异步清零功能的十进制计数器。计数器时钟clk上升沿有效、清零端CLRN、进位输出co。 答：library ieee;use ieee

15、.std_logic_1164.all;entity counter10 isport(clk,CLRN:in std_logic; dout:out integer range 0 to 9);end counter10; （5）architecture behav of counter10 ISbeginprocess(clk)variable cnt:integer range 0 to 9; （3）beginIF CLRN='0' THENCNT:=0;ELSIF clk='1'and clk'event thenif cnt=9 thencnt

16、:=0;elsecnt:=cnt+1;end if;end if;dout<=cnt;end process;end behav; （7）31）用VHDL语言编写半加器和或门器件的程序，如图所示： 答 ：半加器程序：library ieee;use ieee.std_logic_1164.all;entity h_adder isport(a,b:in std_logic; co,so:out std_logic);end h_adder; （2）architecture one of h_adder isbegin so<=not(a xor(not b); co<=a a

17、nd b;end one; （3）或门程序：library ieee;use ieee.std_logic_1164.all;entity or2a is port(a,b:in std_logic; c:out std_logic);end or2a; （2）architecture one of or2a isbeginc<=a or b;end one; 2）在上道题目的基础上用元件例化语句设计1位全加器。主程序：library ieee;use ieee.std_logic_1164.all;entity f_adder is port(ain,bin,cin:in std_lo

18、gic; cout,sum:out std_logic);end entity f_adder;architecture fd1 of f_adder is component h_adder port(a,b:in std_logic; co,so:out std_logic); end component; （5） component or2a port(a,b:in std_logic; c:out std_logic); end component; signal d,e,f:std_logic; begin u1 : h_adder port map(a=>ain,b=>

19、bin,co=>d,so=>e); u2 : h_adder port map(a=>e,b=>cin,co=>f,so=>sum); u3 : or2a port map(d,f,cout);end fd1; （5）1. 试用VHDL语言编程实现一个总线开关，其真值表如下：输 入输 出enselectA0A6B0B6Y0Y60x“ZZZZZZZ”10A11B 1. 总线开关的参考程序如下：LIBRARY ieee;USE ieee.std_logic_1164.all; (1)ENTITY aaa IS PORT( en, select : IN STD_

20、LOGIC ; A, B : IN STD_LOGIC_VECTOR(6 DOWNTO 0 ) ; Y : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) END aaa ; (4)ARCHITECTURE ar OF aaa ISBEGIN PROCESS(en, select ) BEGIN IF en=0 THEN Y<=”ZZZZZZZ”; ELSIF en=1 THEN IF select=0 THEN Y<=A; ELSIF select=1 THEN Y<=B; END IF; END IF ; END PROCESS ;END ar ; (5

21、)2. 试用VHDL语言编程实现一个M10计数器，要求该计数器有一个时钟输入端clk，一个复位端rst（低电平复位），一个使能端en（高电平时允许计数），一个“计数到”输出端cout，一个4位二进制当前计数值输出口q；cout端仅当计数满的一个时钟周期输出高电平，其余时刻全保持低电平。2. M10计数器参考程序：LIBRARY ieee; USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all; （1）ENTITY aaa IS PORT(clk, rst, en : IN

22、 STD_LOGIC; cout: OUT STD_LOGIC; q: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);END aaa; (4)ARCHITECTURE bd OF aaa IS BEGIN PROCESS(clk,reset,en) BEGIN IF (rst='0') THEN q<="0000" ELSIF (clk'event AND clk='1') THEN IF en=1 THEN IF (q=9) THEN q<="0000" ELSE q<

23、=q+1; END IF; END IF; END IF; END PROCESS;END bd; (10)3请用VHDL语言编程，用一个状态机模型实现一个七段码LED字符发生器。该电路有一个复位输入端RST，一个时钟输入端CP，一组七段码输出端ag。在LED上七个段的排列位置如图所示。该电路的功能为，当复位输入端RST为低电平时，输出端口输出全零，无显示；当RST为高电平时，在时钟信号CP的每个上升沿，输出端依次轮流输出5个字符“HAPPY”的七段码（共阴极接法），周而复始。 3. 用VHDL语言编程实现一个LED字符发生器参考程序：LIBRARY ieee;USE ieee.std_log

24、ic_1164.ALL;ENTITY genc IS(1) PORT( rst, cp: IN STD_LOGIC; a,b,c,d,e,f,g: OUT STD_LOGIC );(1)END genc;ARCHITECTURE aa OF genc IS TYPE state IS(s0,s1, s2, s3, s4, s5 ); SIGNAL pstate: state; SIGNAL dout: STD_LOGIC_VECTOR(6 DOWNTO 0 ); （2）BEGIN pr1: PROCESS(cp, rst,) BEGIN IF rst='0' THEN psta

25、te <=s0; ELSIF （cp'event AND cp='0' ） THEN CASE pstate IS WHEN s0=> pstate <=s1;WHEN s1=> pstate <=s2; WHEN s2=> pstate <=s3; WHEN s3=> pstate <=s4; WHEN s4=> pstate <=s5; WHEN s5=> pstate <=s1;WHEN OTHERS=> pstate <=s0; END CASE;END IF; END P

26、ROCESS; （5） pr2: PROCESS(pstate) BEGIN CASE state IS WHEN s0 => dout<="" -无显示WHEN s1 => dout<="" -“H” WHEN s2 => dout<="" -“A” WHEN s3 => dout<="" -“P” WHEN s4 => dout<="" -“P” WHEN s5 => dout<="" -“Y” WH

27、EN OTHERS=> dout<=""-无显示 END CASE; END PROCESS; （5） a<=dout(6); b<=dout(5); c<=dout(4); d<=dout(3); e<=dout(2); f<=dout(1); g<=dout(0);END aa; （1）2试用VHDL语言和进程语句，编程实现一个3-8译码器。该译码器的功能为，当使能信号EN为低电平时，输出端Y7Y0全为高电平（没有输出端被选中）；当EN为高电平时，每一种ABC的输入状态组合能惟一地选中一路输出（被选中的端输出低电平）

28、。真值表如下：输 入输 出ABCENY7Y6Y5Y4Y3Y2Y1Y0000111111110001111111101010111111011011111110111100111101111101111011111110110111111111101111111×××011111111 LIBRARY ieee; USEieee.std_logic_1164.ALL;2ENTITYym38IS1PORT(a, b, c, en:INstd_logic; y:OUTstd_logic_vector(7 DOWNTO 0 );3);ENDym38; ARCHITECTU

29、REarc38OFls273IS1BEGINPROCESS ( en )1SIGNALdin:std_logic_vector(7 DOWNTO 0 );1BEGINdin<=a&b&c&en; 1WITHdinSELECTy<=”WHEN“0001”;”WHEN“0011”;”WHEN“0101”;”WHEN“0111”;”WHEN“1001”;”WHEN“1011”;”WHEN“1101”;”WHEN“1111”;5”WHENOTHERS;ENDPROCESS;ENDarc38;1. 试用VHDL语言编程实现一个多路开关。该电路的功能为，当选择端S0和S

30、1为不同状态组合时，如果使能信号EN为电平，输出端X和Y分别与不同的输入通道A0B0、A1B1、A2B2和A3B3接通并保持，当EN为低电平时，X、Y输出为高阻态。真值表如下：输 入输 出S1S0ENA0B0A1B1A2B2A3B3XY001××××××××A0B0011××××××××A1B1101××××××××A2B2111××&#

31、215;×××××A3B3××0××××××××ZZ1. 多路开关的参考程序如下：LIBRARY ieee; USEieee.std_logic_1164.ALL;ENTITYmulkeyISPORT(s0,s1,en, a0,b0,a1,b1,a2,b2,a3,b3:INstd_logic; x,y:OUTstd_logic_vector(7 DOWNTO 0 );3);ENDmulkey; ARCHITECTUREarmkOFmulkeyIS

32、SIGNAL sel: std_logic_vecter (1 DOWNTO 0 )BEGIN sel<=s1&s0; 2PROCESS (en )BEGINIF (en=0)THENx<=Z;y<=Z; ELSEIF (sel=”00”) THEN x<=a0 ;y<=b0; ELSEIF (sel=”01”) THEN x<=a1 ;y<=b1; ELSEIF (sel=”10”) THEN x<=a2;y<=b2; ELSEIF (sel=”11”) THEN x<=a3 ;y<=b3; END IF;ENDPRO

33、CESS;ENDarmk; 六、写VHDL程序：（10分）1. 设计10进制加法计数器，要求含异步清0和同步时钟使能。注意：时钟信号命名为CLK，使能信号为EN，清零信号为RST，计数输出为CQ。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 IS PORT (CLK,RST,EN : IN STD_LOGIC; CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END CNT10;ARCHITE

34、CTURE behav OF CNT10 ISBEGIN PROCESS(CLK, RST, EN) VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF RST = '1' THEN CQI := (OTHERS =>'0') ; -计数器异步复位 ELSIF CLK'EVENT AND CLK='1' THEN -检测时钟上升沿 IF EN = '1' THEN -检测是否允许计数（同步使能） IF CQI < 9 THEN CQI := CQI + 1

35、; -允许计数, 检测是否小于9 ELSE CQI := (OTHERS =>'0'); -大于9，计数值清零 END IF; END IF; END IF; IF CQI = 9 THEN COUT <= '1' -计数大于9，输出进位信号 ELSE COUT <= '0' END IF; CQ <= CQI; -将计数值向端口输出 END PROCESS;END behav; 2.试描述一个带进位输入、输出的8位全加器端口：A、B为加数，CIN为进位输入，S为加和，COUT为进位输出LIBRARY IEEE;USE I

36、EEE.STD_LOGIC_1164.ALL;ENTITY ADDER8 ISPORT (A, B : IN STD_LOGIC_VECTOR (7 DOWNTO 0); CIN : IN STD_LOGIC; COUT : OUT STD_LOGIC; S : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );END ADDER8;ARCHITECTURE ONE OF ADDER8 ISSIGNAL TS : STD_LOGIC_VECTOR (8 DOWNTO 0);BEGINTS <= (0 & A) + (0 & B) + CIN;S &l

37、t;= TS(7 DOWNTO 0);COUT <= TS(8);END ONE;七、VHDL程序设计：（20分）设计一数据选择器MUX,其系统模块图和功能表如下图所示。试采用下面三种方式中的两种来描述该数据选择器MUX的结构体。(a) 用if语句。 (b) 用case 语句。 (c) 用when else 语句。Library ieee;Use ieee.std_logic_1164.all;Entity mymux isPort (sel : in std_logic_vector(1 downto 0);- 选择信号输入Ain, Bin : in std_logic_vector(

38、1 downto 0);- 数据输入Cout : out std_logic_vector(1 downto 0) );End mymux;Architecture one of mymux isBeginProcess (sel, ain, bin)BeginIf sel = “00” then cout <= ain and bin; Elsif sel = “01” then cout <= ain xor bin;Elsif sel = “10” then cout <= not ain;Else cout <= not bin;End if;End proce

39、ss;End one;Architecture two of mymux isBeginProcess (sel, ain, bin)BeginCase sel iswhen “00” => cout <= ain and bin; when “01” => cout <= ain xor bin;when “10” => cout <= not ain;when others => cout <= not bin;End case;End process;End two;Architecture three of mymux isBeginCo

40、ut <= ain and bin when sel = “00” elseAin xor bin when sel = “01” elseNot ain when sel = “10” else not bin;End three;设计一个7段数码显示译码器，并逐行进行解释LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DECL7S IS PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ; END ; AR

41、CHITECTURE one OF DECL7S IS BEGIN PROCESS( A ) BEGIN CASE A IS WHEN "0000" => LED7S <= "" ; WHEN "0001" => LED7S <= "" ; WHEN "0010" => LED7S <= "" ; WHEN "0011" => LED7S <= "" ; WHEN "0100&q

42、uot; => LED7S <= "" ; WHEN "0101" => LED7S <= "" ; WHEN "0110" => LED7S <= "" ; WHEN "0111" => LED7S <= "" ; WHEN "1000" => LED7S <= "" ; WHEN "1001" => LED7S <= &q

43、uot;" ; WHEN "1010" => LED7S <= "" ; WHEN "1011" => LED7S <= "" ; WHEN "1100" => LED7S <= "" ; WHEN "1101" => LED7S <= "" ; WHEN "1110" => LED7S <= "" ; WHEN "1

44、111" => LED7S <= "" ; WHEN OTHERS => NULL ; END CASE ; END PROCESS ; END ; 关于数据选择器饿设计1、4选1多路选择器的IF语句描述library ieee;use ieee.std_logic_1164.all;entity multiplexers_1 isport (a, b, c, d : in std_logic;s : in std_logic_vector (1 downto 0);o : out std_logic);end multiplexers_1;ar

45、chitecture archi of multiplexers_1 isbeginprocess (a, b, c, d, s)beginif (s = "00") then o <= a;elsif (s = "01") then o <= b;elsif (s = "10") then o <= c;else o <= d;end if;end process;end archi;2、4选1多路选择器的CASE语句描述library ieee;use ieee.std_logic_1164.all;entity multiplexers_2 isport (a, b, c, d : in std_logic; s : in std_logic_vector (1 downto 0); o : out std_l