EDA课程设计八路彩灯控制器

1、EDA课程设计设计题目：基于VHDL的8路彩灯控制器设计一、 课程设计的目的1 熟悉Quartus软件的使用方法,使用VHDL 文本输入设计法进行任务设计。2 增强自己实际动手能力,独立解决问题的能力。3 通过课程设计对所学的知识进行更新及巩固.二、 课程设计的基本要求本次课程设计是设计一个8路彩灯控制器，能够控制8路彩灯按照两种节拍，三种花型循环变化。设计完成后，通过仿真验证与设计要求进行对比，检验设计是否正确。三、 课程设计的内容编写硬件描述语言VHDL程序，设计一个两种节拍、三种花型循环变化的8路彩灯控制器，两种节拍分别为0.25s和0.5s。三种花型分别是：（1）8路彩灯分成两半，从左

2、至右顺次渐渐点亮，全亮后则全灭。（2） 从中间到两边对称地渐渐点亮，全亮后仍由中间向两边逐次熄灭。（3） 8路彩灯从左至右按次序依次点亮，全亮后逆次序依次熄灭。四、 实验环境 PC机一台；软件Quartus6.0五、课程设计具体步骤及仿真结果1、系统总体设计框架结构分频模块：把时钟脉冲二分频，得到另一个时钟脉冲，让这两种时钟脉冲来交替控制花型的速度。二选一模块：选择两种频率中的一个控制彩灯的花型。8路彩灯的三种花型控制模块：整个系统的枢纽，显示彩灯亮的情况。2、系统硬件单元电路设计1.分频模块设计实验程序：library ieee;use ieee.std_logic_1164.all;ent

3、ity fenpin2 is port( clk:in std_logic; clkk:out std_logic);end fenpin2;architecture behav of fenpin2 isbegin process(clk) variable clkk1:std_logic:='0' begin if clk'event and clk='1' then clkk1:= not clkk1; end if; clkk<=clkk1; end process;end behav;RTL电路图：波形图：2.二选一模块设计实验程序：li

4、brary ieee;use ieee.std_logic_1164.all;entity mux21 isport(a,b,s:in std_logic; y:out std_logic);end mux21;architecture behave of mux21 isbeginprocess(a,b,s)beginif s='0' then y<=a;else y<=b;end if;end process;end behave;RTL电路图：波形图：3.8路彩灯的三种花型控制模块设计程序: library ieee;use ieee.std_logic_11

5、64.all;use ieee.std_logic_unsigned.all;entity color8 isport(clk,rst :in std_logic; q:out std_logic_vector(7 downto 0);end;architecture a of color8 issignal s:std_logic_vector(4 downto 0);beginprocess(s,clk)beginif rst='1' then s<="00000"elsif clk'event and clk= '1' t

6、henif s="11111" then s<="00000"else s<=s+1;end if;case s iswhen "00000"=>q<="00000000"when "00001"=>q<="10001000"when "00010"=>q<="11001100"when "00011"=>q<="11101110"whe

7、n "00100"=>q<="11111111"when "00101"=>q<="00000000"when "00110"=>q<="00011000"when "00111"=>q<="00111100"when "01000"=>q<="01111110"when "01001"=>q<="

8、;11111111"when "01010"=>q<="11100111"when "01011"=>q<="11000011"when "01100"=>q<="10000001"when "01101"=>q<="00000000"when "01110"=>q<="10000000"when "01111&quo

9、t;=>q<="11000000"when "10000"=>q<="11100000"when "10001"=>q<="11110000"when "10010"=>q<="11111000"when "10011"=>q<="11111100"when "10100"=>q<="11111110"wh

10、en "10101"=>q<="11111111"when "10110"=>q<="11111110"when "10111"=>q<="11111100"when "11000"=>q<="11111000"when "11001"=>q<="11110000"when "11010"=>q<=&quo

11、t;11100000"when "11011"=>q<="11000000"when "11100"=>q<="10000000"when "11101"=>q<="00000000"when others=>null;end case;end if;end process; end;RTL电路图：波形图：4.综合程序library ieee;use ieee.std_logic_1164.all;entity fenpin

12、2 is port( clk:in std_logic; clkk:out std_logic);end fenpin2;architecture behav of fenpin2 isbegin process(clk) variable clkk1:std_logic:='0' begin if clk'event and clk='1' then clkk1:= not clkk1; end if; clkk<=clkk1; end process;end behav;library ieee;use ieee.std_logic_1164.

13、all;entity mux21 isport(a,b,s:in std_logic; y:out std_logic);end mux21;architecture behave of mux21 isbeginprocess(a,b,s)beginif s='0' then y<=a;else y<=b;end if;end process;end behave;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity color8 isport(clk,rst

14、 :in std_logic; q:out std_logic_vector(7 downto 0);end;architecture a of color8 issignal s:std_logic_vector(4 downto 0);beginprocess(s,clk)beginif rst='1' then s<="00000"elsif clk'event and clk= '1' thenif s="11111" then s<="00000"else s<=s+

15、1;end if;case s iswhen "00000"=>q<="00000000"when "00001"=>q<="10001000"when "00010"=>q<="11001100"when "00011"=>q<="11101110"when "00100"=>q<="11111111"when "00101&

16、quot;=>q<="00000000"when "00110"=>q<="00011000"when "00111"=>q<="00111100"when "01000"=>q<="01111110"when "01001"=>q<="11111111"when "01010"=>q<="11100111"

17、;when "01011"=>q<="11000011"when "01100"=>q<="10000001"when "01101"=>q<="00000000"when "01110"=>q<="10000000"when "01111"=>q<="11000000"when "10000"=>q<=&

18、quot;11100000"when "10001"=>q<="11110000"when "10010"=>q<="11111000"when "10011"=>q<="11111100"when "10100"=>q<="11111110"when "10101"=>q<="11111111"when "10110

19、"=>q<="11111110"when "10111"=>q<="11111100"when "11000"=>q<="11111000"when "11001"=>q<="11110000"when "11010"=>q<="11100000"when "11011"=>q<="11000000"when "11100"=>q<="10000000"when "11101"=>q<="00000000"when others=>null;end case;end if;en