北航电子电路设计数字部分实验报告

1、电子电路设计数字部分实验报告学院:姓名:实验一简单组合逻辑设计实验内容描述一个可综合的数据比较器，比较数据a、b的大小，若相同，则给出结果1,否则给出结果0。实验仿真结果实验代码主程序modulecompare(equal,a,b);input7:0a,b;outputequal;assignequal=(ab)1:0;endmodule测试程序modulet;reg7:0a,b;regclock,k;wireequal;initialbegina=0;b=0;clock=0;k=0;endalways#50clock=clock;always(posedgeclock)begina0=$ra

2、ndom%2;a1=$random%2;a2=$random%2;a3=$random%2;a4=$random%2;a5=$random%2;a6=$random%2;a7=$random%2;b0=$random%2;b1=$random%2;b2=$random%2;b3=$random%2;b4=$random%2;b5=$random%2;b6=$random%2;b7=$random%2;endinitialbegin#100000$stop;endcomparem(.equal(equal),.a(a),.b(b);endmodule实验二简单分频时序逻辑电路的设计实验内容用al

3、ways块和(posedgeclk)或(negedgeclk)的结构表述一个1/2分频器的可综合模型,观察时序仿真结果。实验仿真结果盯fiwn1m用聃溺wMeeh*0国.w实验代码主程序modulehalf_clk(reset,clk_in,clk_out);inputclk_in,reset;outputclk_out;regclk_out;always(negedgeclk_in)beginif(!reset)clk_out=0;elseclk_out=clk_out;endendmodule测试程序timescale1ns/100Psdefineclk_cycle50moduletop;

4、regclk,reset;wireclk_out;always#clk_cycleclk=clk;initialbeginclk=0;reset=1;#10reset=0;#110reset=1;#100000$stop;endhalf_clkm0(.reset(reset),.clk_in(clk),.clk_out(clk_out);endmodule实验三利用条件语句实现计数分频时序电路实验内容利用10MHz的时钟，设计一个单周期形状的周期波形。实验仿真结果卧f241VH用臼实验代码主程序modulefdivision(RESET,F10M,out);inputF10M,RESET;ou

5、tputout;regout;reg7:0i;always(posedgeF10M)if(!RESET)beginout=0;i=0;endelseif(i=2|i=3)beginout=out;i=i+1;endelseif(i=5)i=1;elsei=i+1;endmodule测试程序timescale1ns/100Psmoduledivision_top;regF10M,RESET;wireout;always#50F10M=F10M;initialbeginRESET=1;F10M=0;#90RESET=0;#100RESET=1;#10000$stop;endfdivisionfdi

6、vision(.RESET(RESET),.F10M(F10M),.out(out);endmodule实验四阻塞赋值与非阻塞赋值的区别实验内容比较四种不同的写法，观察阻塞与非阻塞赋值的区别。Blocking:always(posedgeclk)beginb=a;c=b;endBlocking1always(posedgeclk)beginc=b;b=a;endBlocking2:always(posedgeclk)b=a;always(posedgeclk)c=b;non_Blocking:always(posedgeclk)beginb=a;c=b;End实验仿真结果tjirf5口口息r7

7、田行国，4-实验代码主程序moduleblocking(clk,a,b,c);output3:0b,c;input3:0a;inputclk;reg3:0b,c;always(posedgeclk)beginb=a;c=b;endendmodule测试部分timescale1ns/100psinclude./include./include./include./modulecompareTop;Wire3:0b11,c11,b12,c12,b13,c13,b2,c2;reg3:0a;regclk;initialbeginclk=0;forever#50clk=clk;endinitialbeg

8、ina=4h3;$display(%d,a);#100a=4h7;$display(%d,a);#100a=4hf;$display(%d,a);#100a=4ha;$display(%d,a);#100a=4h2;$display(%d,a);#100$stop;endblockingblocking(clk,a,b11,c11);blocking1blocking1(clk,a,b12,c12);blocking2blocking2(clk,a,b13,c13);non_blockingnon_blocking(clk,a,b2,c2);endmodule实验五用always块实现较复杂的

9、组合逻辑实验目的运用always块设计一个8路数据选择器。要求：每路输入数据与输出数据均为4位2进制数，当选择开关（至少3位）或输入数据发生变化时，输出数据也相应地变化。实验仿真结果实验代码主程序modulealu(out,opcode,a1,a2,a3,a4,a5,a6,a7,a8);output3:0out;reg3:0out;input3:0a0,a1,a2,a3,a4,a5,a6,a7;input2:0opcode;always(opcodeoralora2ora3ora4ora5ora6ora7ora0)begincase(opcode)3d0:out=a0;3d1:out=a1;3

10、d2:out=a2;3d3:out=a3;3d4:out=a4;3d5:out=a5;3d6:out=a6;3d7:out=a7;default:out=4b0000;endcaseendendmodule测试程序timescale1ns/1nsinclude./modulealutext;wire3:0out;reg3:0a1,a2,a3,a4,a5,a6,a7,a8;reg2:0opcode;initialbegina1=$random%16;a2=$random%16;a3=$random%16;a4=$random%16;a5=$random%16;a6=$random%16;a7=$

11、random%16;a8=$random%16;repeat(100)begin#100opcode=$random%8;a1=$random%16;a2=$random%16;a3=$random%16;a4=$random%16;a5=$random%16;a6=$random%16;a7=$random%16;a8=$random%16;end#100$stop;endalualu(out,opcode,a1,a2,a3,a4,a5,a6,a7,a8);endmodule实验六在VerilogHDL中使用函数实验目的设计一个带控制端的逻辑运算电路，分别完成正整数的平方、立方和最大数为5的

12、阶乘运算。实验仿真结果实验代码主程序moduletryfunct(clk,n,result1,result2,result3,reset);output31:0result1,result2,result3;input3:0n;inputreset,clk;reg31:0result1,result2,result3;always(posedgeclk)beginif(!reset)beginresult1=0;result2=0;result3=0;endelsebeginresult1=fun1(n);result2=fun2(n);result3=fun3(n);endendfuncti

13、on31:0fun1;input3:0operand;fun1=operand*operand;endfunctionfunction31:0fun2;input3:0operand;beginfun2=operand*operand;fun2=operand*fun2;endendfunctionfunction31:0fun3;input3:0operand;reg3:0index;beginfun3=1;if(operand11)for(index=2;index=operand;index=index+1)fun3=index*fun3;elsefor(index=2;index=10

14、;index=index+1)fun3=index*fun3;endendfunctionendmodule测试程序include./timescale1ns/100PsmoduletryfunctTop;reg3:0n,i;regreset,clk;wire31:0result1,result2,result3;initialbeginclk=0;n=0;reset=1;#100reset=0;#100reset=1;for(i=0;iy)begintmp=x;x=y;y=tmp;endendtaskendmodule测试部分1timescale1ns/100Psincludemodulet

15、ask_Top;reg7:0a,b,c,d;wire7:0ra,rb,rc,rd;initialbegina=0;b=0;c=0;d=0;repeat(50)begin#100a=$random%255;b=$random%255;c=$random%255;d=$random%255;end#100$stop;endrankrank(.ra(ra),.rb(rb),.rc(rc),.rd(rd),.a(a),.b(b),.c(c),.d(d);endmodule主程序2modulerank(a,rst,clk,ra,rb,rc,rd);output7:0ra,rb,rc,rd;input7:

16、0a;inputclk,rst;reg7:0ra,rb,rc,rd;reg7:0va,vb,vc,vd;reg3:0i;always(posedgeclkornegedgeclk)beginif(!rst)beginva=0;vb=0;vc=0;vd=0;i=0;endelsebeginif(iy)begintmp=x;x=y;y=tmp;endendtaskendmodule测试部分2timescale1ns/100Psincludemoduletask_Top;reg7:0a;wire7:0ra,rb,rc,rd;regclk,rst;initialbegina=0;rst=0;clk=0

17、;#50rst=1;#100a=8$random;#100a=8$random;#100a=8$random;#100a=8$random;#100a=8$random;#100a=8$random;#100a=8$random;#100a=8$random;#100$stop;endalways#100clk=clk;rankrank(.a(a),.rst(rst),.clk(clk),.ra(ra),.rb(rb),.rc(rc),.rd(rd);endmodule实验八利用有限状态机进行时序逻辑的设计实验目的设计一个串行数据检测器。要求连续四个或四个以上为1时输出1,其他输入情况下为0.

18、实验仿真结果实验代码主程序moduleseqdet(x,z,clk,rst,state);inputx,clk,rst;outputz;output2:0state;reg2:0state;wirez;parameterIDLE=d0,A=d1,B=d2,C=d3,D=d4;assignz=(state=D&x=1)1:0;always(posedgeclk)if(!rst)beginstate=IDLE;endelsecasex(state)IDLE:if(x=1)beginstate=A;endA:if(x=1)beginstate=B;endelsebeginstate=IDLE;end

19、B:if(x=1)beginstate=C;endelsebeginstate=IDLE;endC:if(x=1)beginstate=D;endelsebeginstate=IDLE;endD:if(x=1)beginstate=D;endelsebeginstate=IDLE;enddefault:state=IDLE;endcaseendmodule测试代码includemoduleseqdet_Top;regclk,rst;reg23:0data;wire2:0state;wirez,x;assignx=data23;always#10clk=clk;always(posedgeclk

20、)data=data22:0,data23;initialbeginclk=0;rst=1;# 2rst=0;# 30rst=1;data=b1001_1111_0111_1110;# 500$stop;endseqdetm(x,z,clk,rst,state);endmodule实验九楼梯灯实验目的楼下到楼上依次有3个感应灯：灯1、灯2、次T3。当行人上下楼梯时，各个灯感应到后自动点亮，若在8s内感应信号消失，则点亮8s,若感应信号存在时间超过8s,则感应信号消失4s后灯自动关闭。任务1:做出如上逻辑电路设计并仿真；任务2:考虑去抖情况，对于感应信号到达存在毛刺（小于，设计合适逻辑并剔出。任

21、务3:若为节约能源，下一个灯点亮的同时将自动关闭上一个灯，做出如上逻辑设计并仿真（仅考虑一个人的情况）实验仿真结果实验代码主程序modulelight_All(clk10,rst,switch,light);inputclk10,rst;input2:0switch;output2:0light;reg2:0state1,state2,state3;reg7:0count1,count2,count3;reg2:0count_1,count_2,count_3;reg2:0light;parameterstate1_start=3b000,state2_start=3b000,state3_s

22、tart=3b000,state1_work=3b001,state2_work=3b001,state3_work=3b001,state1_up=3b010,state2_up=3b010,state3_up=3b010,state1_down=3b011,state2_down=3b011,state3_down=3b011,state1_other=3b100,state2_other=3b100,state3_other=3b100;always(posedgeclk10)if(!rst)beginstate1=state1_start;count1=8b0;count_1=3b0;

23、endelseif(switch0=b1&count_14)count_1=count_1+1;elsecase(state1)state1_start:if(switch0=b1)beginstate1=state1_up;count1=78;elsebeginstate1=state1_start;light00)begincount1=count1-1;if(switch0=b0&(state2=3b010|state3=3b010)beginlight0=b0;state1=state1_down;endendelseif(switch0=b0)beginstate1=state1_d

24、own;endelsebeginstate1=state1_other;count1=39;endstatelother:if(switch0=b1)state10)begincount1=count1-1;if(switch0=b0&(state2=3b010|state3=3b010)beginlight0=b0;state1=state1_down;endendelsestate1=state1_down;state1_down:beginlight0=b0;count_1=3b0;state1=state1_start;endstate1_up:beginlight0=b1;state

25、1=state1_work;enddefault:state1=state1_start;endcasealways(posedgeclk10)if(!rst)beginstate2=state2_start;count2=8b0;count_2=3b0;endelseif(switch1=b1&count_24)count_2=count_2+1;elsecase(state2)state2_start:if(switch1=b1)beginstate2=state2_up;count2=78;endelsebeginstate2=state2_start;light10)begincoun

26、t2=count2-1;if(switch1=b0&(state1=3b010|state3=3b010)beginlight1=b0;state2=state2_down;endendelseif(switch1=b0)beginstate2=state2_down;endelsebeginstate2=state2_other;count2=39;endstate2other:if(switch1=b1)state20)begincount2=count2-1;if(switch1=b0&(state1=3b010|state3=3b010)beginlight1=b0;state2=st

27、ate2_down;endendelsestate2=state2_down;state2_down:beginlight1=b0;count_2=3b0;state2=state2_start;endstate2_up:beginlight1=b1;state2=state2_work;endenddefault:state2=state2_start;endcasealways(posedgeclk10)if(!rst)beginstate3=state3_start;count3=8b0;count_3=3b0;endelseif(switch2=b1&count_34)count_3=

28、count_3+1;elsecase(state3)state3_start:if(switch2=b1)beginstate3=state3_up;count3=78;endelsebeginlight20)begincount3=count3-1;if(switch2=b0&(state1=3b010|state2=3b010)beginlight2=b0;state3=state3_down;endendelseif(switch2=b0)beginstate3=state3_down;endelsebeginstate3=state3_other;count3=39;endstate3

29、_other:if(switch2=b1)state30)begincount3=count3-1;if(switch2=b0&(state1=3b010|state2=3b010)beginlight2=b0;state3=state3_down;endendelsestate3=state3_down;state3_down:beginlight2=b0;count_3=3b0;state3=state3_start;endstate3_up:beginlight2=b1;state3=state3_work;enddefault:endcaseendmodule测试程序timescale100ns/10nsmoduletest_light_All;regclk10,rst;reg2:0up,down;wire2:0swh;wire2:0light;parameter