键盘扫描与计算器VHDL仿真设计

1、简易计算器设计EDA实验报告实验内容实验要求：完成个位数的加减乘运算，输入用矩阵键盘,输出用数码管显示，每输入一次数据要显示在数码管上。矩阵键盘共16个按键，用其中10个做个位数的输入，用3个分别做加减乘运算，用其中1个做等于操作，各位数的运算结果最 多两位，用动态扫描数码管显示运算结果。二、小组成员三、实现方法系统组成及连接原理如图所示 ，主要由由七个功能模块组成 ：分频模块（为键盘扫 描模块和防抖模块提供时钟 ）、键盘扫描驱动模块 （依次置零）、键盘按键值编码 模块、键盘编码值防抖模块、运算模块，数码管显示驱动模块、动态扫描驱动模 块。数码 管显 4运算动态 显示1fI-11分频模块由于F

2、PGA实验板的原始时钟频率高达33.8688MHz，所以不能直接接入设计模块中使用，就需要用到分频模块。将33.8688MHz分频到4KHz和10Hz来使用，一个用于行驱动扫描时钟，一个用于防抖模块。所以，采用写一个可变分频元件来调用。元件视图：elkclkout_kbclkout_LED主要代码如下 （完整代码见附录，下同）：architecture RTL of freq_divisi on iscomp onent frediv n isgen eric (n:positive);Port ( clki n:in STD_LOGIC;clkout:out STD_LOGIC);end c

3、omp onent;beginU1:frediv ngen eric map( n=>3)port map(clk in=>clk,clkout=>clkout_kb);end RTL;仿真结果如下图：达到预期的目的2.行驱动模块（依次对行置零）：键盘扫描的原理就是检测行列信号然后判断出具体是按下了哪一个按键。所以，对行依次置零，当置零频率较快时，按下某一个按键后，一定能得到某一列的信号输出为零，如下图：keyin上拉电阻孑wrjhmIDwwwCDEkeydrAv*89A_k456*012当行信号为1110时，若按下了 0键，就会得到1110的列信号,立马就快可以译码出 按键

4、值，若按下4键、8键、C键则都不会有输出。主要代码如下：process(clk in)beginif clr='1' the ncou nt<="00"elsif rising_edge(clkin) thenif coun t="11" the ncou nt<="00"else coun t<=co un t+1;end if;end if;end process;process(co unt)beginif cou nt="01" thenkeydrv<="1

5、110"elsif coun t="10" thenkeydrv<="1101"elsif coun t="11" thenkeydrv<="1011"elsif coun t="00" thenkeydrv<="0111"end if;end process;仿真结果如下图：达到预期的目的3.键值编码模块依据行驱动模块，当按下某一个按键后，立马可以根据行列和并位信号得到唯一的键盘编码值，用5位矢量来保存结果，当没有按键按下时，编码值一直保持着11

6、111不变, 并在后端的模块中不对其做任何处理。以下列出部分编码表（完整编码表见附录）十进制数行&列HEX七段码HEX011101110EE11111107E411011110DE011001133511011101DD10110115B主要代码如下process(clk)beginif clr='0' thenif risin g_edge(clk) the nif temp仁"11101110" the nkeyvalue1<="00000"-0elsif temp仁"11101101" the nk

7、eyvalue1<="00001"-1elsif temp1="11101011" the nkeyvalue1<="00010"-2elsif temp1="11100111" the nkeyvalue1<="00011"-3elsif temp1="11011110" the nkeyvalue1<="00100"-4elsif temp1="11011101" the nkeyvalue1<=&qu

8、ot;00101"-5elsif temp1="11011011" the nkeyvalue1<="00110"-6elsif temp1="11010111" the nkeyvalue1<="00111"-7elsif temp1="10111110" the nkeyvalue1<="01000"-8elsif temp1="10111101" the nkeyvalue1<="01001"-9

9、elsif temp1="10111011" the nkeyvalue1<="01010"-10elsif temp仁"10110111" the nkeyvalue1<="01011"-11elsif temp仁"01111110" the nkeyvalue1<="01100"-12elsif temp1="01111101" the nkeyvalue1<="01101"-13elsif temp1=&q

10、uot;01111011" the nkeyvalue1<="01110"-14elsif temp1="01110111" the nkeyvalue1<="01111"-15end if;end if;end if;end process;波形仿真如下图：4防抖模块键盘按键物理模型如下通常的按键所用开关为机械弹性开关，当机械触点断开、闭合时，由于机械触点的弹性作用，一个按键开关在闭合时不会马上稳定地接通，在断开时也不会一下子断开。因而在闭合及断开的瞬间均伴随有一连串的抖动，为了不产生这种现象而作的措施就是按键

11、消抖。抖动时间的长短由按键的机械特性决定，一般为5ms10ms。一般来说，软件消抖的方法是不断检测按键值,直到按键值稳定。实现方法：假设未按键时输入1,按键后输入 为0,抖动时不定。可以做以下检测：检测到按键输入为 0之后，延时5ms10ms ,再次 检测，如果按键还为0,那么就认为有按键输入。延时的5ms10ms恰好避开了抖动 期。本模块是采用多次采样来达到防抖的，只有在给定的采样次数内，都保证采样结果一致时才会输出按键编码值。主要代码如下：case count iswhen "0000"=> test1<=temp;when "0001"

12、=> test2<=temp;when "0010"=> test3<=temp;whe n "0011"=> test4<=temp;when "0100"=> test5<=temp; when "0101"=> test6<=temp;when "0110"=> test7<=temp;when "0111"=> test8<=temp;when "1000"=>

13、; test9<=temp;when "1001"=> test10<=temp;when "1010"=> test11<=temp;when "1011"=> test12<=temp;when "1100"=> test13<=temp;when "1101"=> test14<=temp;when "1110"=> test15<=temp;when "1111"=>

14、; test16<=temp;whe n others=>n ull;end case;if test1=test5 and test2=test6 and test3=test7 and test4=test8 and test5=test9 and test6=test10 and test7=test11 and test8=test12 and test9=test13 and test10=test14 and test11=test15 and test12=test16 and testl /= "UUUUUUUU" the n仿真波形如下：从图中

15、可以看出最终tempi从临时信号temp得到最终输出，达到防抖：常护J DJJEIII B113'1! b'i-i£31i|aeF1uu ui I1i15.运算模块当前段的模块经过防抖处理以后得到稳定的按键信号，比如1+2=3,转化为编码值就是11101101 10111011 01111101 11100111 => ED BB EB 7D E7(具体编码表见附录 )主要代码如下：if ysfh=0 the n result<=first+sec ond;elsif ysfh=1 then result<=first-second;elsif ys

16、fh=2 then result<=first*second;end if; n<=n+'1'elsif n="100" the nn<="000"end if;end if;end process;process (n)beginif n=" 001"the n keyvalue in<=con v_stdogic_vector(first,8);elsif n="011"the n keyvalue in<=con v_std_logic_vector(sec on

17、 d,8);elsif n="100"the n keyvalue in<=con v_std_logic_vector(result,8);end if;end process;仿真波形如下以1+3=4 和5x6=30 为例：nr oejiiaiueiii3|1 -L夕；.戸1 Lsie i! " da !i a IE 1 ' £4 afi' 4 1 4* 1汕，弭”'t.£ - * a - > »i4ei-ii4irslart-口 IT縛住阿:DtoOl贰右阿曲同:司习可观!（F何:IC何心:.

18、莎:忙匠價:陋）：耶何阳T側（诚删二 二ir卿nd"同1耐LTJ厂m"那加図问T啷潮醴d丄D1 Urnr郵曲卩1U 1 11_1L1Ennranr7 W 1rnnx 即 alu 訓70|M骨恫UE l7-nr團词騎in冋011|编码：01 + 03 =0405 X 06 =1EIt追怕u"闵w :饋汕測q1"Inr唧创El咂U6.数码管显示模块以及动态扫描模块由于次两个模块是密切相关的，所以统一到一起验证。经过运算得到最终的显示结果后，要在七段数码管中显示，就必须有每一个数的七段码，同时，由于前面的运算模块的结果最大可以达到 81，也就是需要8位二进制，

19、两位十进制来表示，所以就必须通过显示模块来分离出十位和个位。分离出十位和个位以后，就必须要利用动态扫描使两个数都能显示出来。因为8个七段数码管的abcdefg位是连在一起的，只有利用分时间隔来显示，一次使能一个数码管，显示一位数，当频率较高时，就可以得到两位数的显示效果 数码管显示模块主要代码如下：if num=O the nten:=0;on e:=10;elsif num <10 and num >0the nten:=0;one:=num;elsif num <20 and num>9 the nten :=1;o ne:=nu m-10;elsif num &l

20、t;30 and num >19 the nten:=2; one:=nu m-20;elsif num<40 and num >29 the nten:=3; one:=nu m-30;elsif num <50 and num >39 the nten :=4;o ne:=nu m-40;elsif num <60 and num >49 the nten:=5; one:=nu m-50;elsif num <70 and num >59 the nten :=6;o ne:=nu m-60;elsif num <80 and

21、num >69 the nten:=7; one:=nu m-70;elsif num <90 and num >79 the nten:=8; one:=nu m-80;elsif num <100 and num >89 the n ten:=9; one:=nu m-90;end if;t<=c on v_std_logic_vector(te n,4);o<=c on v_std_logic_vect or(on e,4); 动态扫描模块主要代码如下：if coun t="00" the nshowout<=show1

22、;e n<="00000010"elsif coun t="01" the nshowout<=show2;e n<="00000001" end if;仿真波形如下：数码显示模块Show1是十位数，show2是个位数，分别为7E（七段码十六进制）和30,即01 。扫描显示模块数码管使能信号en依次在01和02中变化,翻译成八段码就是00000001和00000010四、模块调用将上述模块按照层次调用，就可以得到最顶层的文件，完成计算器的所有要求功台匕 冃匕。调用图如下时钟模块:分频顶层文件运算模块防抖模块后端 处

23、理扫描显示数码管显示键盘编码最终的仿真波形如下：01 => showout 0110000 3002 => showout 1101101 6D03 => showout 1111001 79由以上波形可以看出：01 + 02 = 03的计算完成了 。五、总结本次EDA设计实践，完成了从 VHDL代码编写到硬件实现的整个流程，掌握了一些FPGA的相关概念以及ISE软件和Active-HDL软件的使用方法。最重要的就是组员之间的 合作，因为VHDL程序是模块化编写的，所以不同模块是由不同人来完成编译的，要达到各个模块之间能够良好的衔接通信，就必须有一个很好的沟通交流，把大家的思

24、路集中起来，一起讨论、编写、调试程序。附录一】完整程序：分频:library IEEE;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_ARITH.ALL;useuseIEEE.STD_LOGIC_UNSIGNED.ALL;IEEE.STD_LOGIC_UNSIGNED.ALL;en tity frediv n isen tity keysca n isgen eric( n:i nteger:=3);Port

25、 ( clr:in std_logic;clki n : inPort ( elk in:in STD_LOGIC;STD_LOGIC;clkout:outkeydrv :outSTD_LOGIC);STD_LOGIC_VECTOR(3 dow nto 0);end frediv n;end keysca n;architecture behavioral ofarchitectureBehavioralofkeysca n isfrediv n issig nal count : std_logic_vector(1sig nal clk1:std_logic:='0：dow nto

26、 0);sig nal coun ter:i nteger range 0 tobeginn;process(clk in)beginbeginprocess(clk in)if clr='1' thencou nt<="00"beginelsif rising_edge(clkin) thenif risin g_edge(clk in) the nif cou nt="11" the nif counter=(n-1)/2 the ncou nt<="OO"elseclk1<=not clk1;c

27、oun t<=co un t+1;coun ter<=0;end if;end if;elseend process;coun ter<=co un ter+1;process(co unt)end if;beginend if;if cou nt="01" the nend process;keydrv<="1110"clkout<=clk1;elsif cou nt="10" the nend Behavioral;keydrv<="1101"elsif cou nt=&qu

28、ot;11" the nkeydrv<="1011"elsif coun t="00" the nkeydrv<="0111"end if;end process;end behavioral;键值编码：防抖：library IEEE;library IEEE;use IEEE.STD_LOGIC_1164.ALL;useuse IEEE.STD_LOGIC_ARITH.ALL;IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_UNSIGNED.ALL;useen tity k

29、eydecoder isIEEE.STD_LOGIC_ARITH.ALL;Port ( clkin,clk,clr: in std_logic;usekeyi n : in STD_LOGIC_VECTOR (3IEEE.STD_LOGIC_UNSIGNED.ALL;dow nto 0);use ieee .nu meric_std.all;keycode : outSTD_LOGIC_VECTORen tity fan gdou is(4 dow nto 0)port(keycode:i n);std_logic_vector(4 dow nto 0);end keydecoder;keyc

30、ode1:outarchitecture Rtl of keydecoder isstd_logic_vector(4 dow nto 0);sig nal temp:STD_LOGIC_VECTOR (7sta rt:out std_logic;dow nto 0);clk_f,clr:in std_logic);sig nal keydrv1:STD_LOGIC_VECTOR (3end fan gdou;dow nto 0);architecture fan gdou ofsig nal keyvalue1:STD_LOGIC_VECTOR (4fan gdou isdow nto 0)

31、;sig nalsig nal temp1:STD_LOGIC_VECTOR (7coun t1:std_logic_vector(2dow nto 0);dow nto 0);comp onent keysca nsig nalPort ( clkin ,clr: inSTD_LOGIC;key1:std_logic_vector(4 dow nto0);keydrv : outSTD_LOGIC_VECTOR(3sig naldow nto 0);key2:std_logic_vector(4 dow ntoend comp onent;0);comp onent fan dou1sig

32、nalPort ( clk in ,clr: inSTD_LOGIC;key3:std_logic_vector(4 dow ntotemp:in std_logic_vector(70);dow nto 0);sig naltemp1: outSTD_LOGIC_VECTOR(7key4:std_logic_vector(4 dow ntodow nto 0);end comp onent;0);beginsig nalu1: keyscankey5:std_logic_vector(4 dow ntoport0);map(clk in=>clk in, keydrv=>keyd

33、rv1,clr=>csig nallr);key6:std_logic_vector(4 dow ntotemp<=keydrv1 &keyi n;0);u2:fa ndou1sig nalport map(clk in=>clk in ,temp=>temp.key7:std_logic_vector(4 dow ntotemp1=>temp1,clr=>clr);0);process(clk)sig nalbeginkey8:std_logic_vector(4 dow ntoif clr='0' then0);if risin

34、g_edge(clk) the nsig nal start_1:std_logic;if temp仁"11101110"beginthe nkeyvalue1<="00000"process(clk_f)elsif temp1="11101101" the nbeginkeyvalue1<="00001"if clr='1' thenelsif temp仁"11101011"the nkeyvalue1<="00010"key1<=&

35、quot;00000"elsif temp仁"11100111"key2<="00001"the nkeyvalue1<="00011"key3<="00010"elsif temp仁"11011110"the nkey4<="00011"keyvalue1<="00100"elsif temp仁"11011101"key5<="00100"the nkeyvalue1&

36、lt;="00101"key6<="00101"elsif temp仁"11011011"the nkey7<="00110"keyvalue1<="00110"elsif temp仁"11010111"key8<="00111"the nkeyvalue1<="00111"cou nt1<="000"elsif temp仁"10111110"start_1&l

37、t;='1'the nkeyvalue1<="01000"elseelsif temp仁"10111101"if risin g_edge(clk_f)the nthe nkeyvalue1<="01001"if cou nt1="111" thenelsif temp仁"10111011"cou nt1<="000"the nelsekeyvalue1<="01010"coun t1<=co un t1+&#

38、39;1'elsif temp1="10110111" the nend if;keyvalue1<="01011"end if;elsif temp仁"01111110"end if;the ncase count1 iskeyvalue1<="01100"whe nelsif temp仁"01111101""000"=>key1<=keycode;the nwhe nkeyvalue1<="01101""

39、001"=>key2<=keycode;elsif temp1="01111011"whe nthe n"010"=>key3<=keycode;keyvalue1<="01110"whe nelsif temp仁"01110111""011"=>key4<=keycode;the nwhe nkeyvalue1<="01111""100"=>key5<=keycode;end if;w

40、he nend if;"101"=>key6<=keycode;end if;whe nend process;"110"=>key7<=keycode;keycode<=keyvalue1;whe nend rtl;"111"=>key8<=keycode; whe n others =>nu II;end case;if key1=key2 and key2=key3and key3=key4 and key4=key5and key5=key6 and key6=key7and k

41、ey7=key8 andkey1/="UUUUU"the nkeycode1<=key1;start_1<='0' after 5ns;end if;end process;start<=start_1;end fan gdou;运算：数码管显示：library IEEE;library IEEE;use IEEE.STD_LOGIC_1164.ALL;useuse IEEE.STD_LOGIC_ARITH.ALL;IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_UNSIGNED.ALL;use iee

42、e.std_logic_arith.all;use ieee .nu meric_std.all;useen tity yun sua n isieee.std_logic_ un sig ned.all;port(start: in std_logic;en tity shumagua nxia nshi iskeycode1:i n std_logic_vector(4 dow nto 0);port(keyvaluei n:i nkeyvaluei n:out stdo gic_vector(7 dow ntostd_logic_vector(7 dow nto 0);0)；clk:in

43、 std_logic;end yun sua n;show1,show2:outarchitecture Behavioral of yun sua n isstd_logic_vector(6 dow nto 0);sig nalfirst,sec on d,result,ysfh:end shumagua nxia nshi ;in teger range 0 to 99;architecturesig naln:stdo gic_vector(2 dow ntoshumagua nxia nshiof0)；shumagua nxia nshi isbeginsig nal t:std_l

44、ogic_vector(3process(start,keycode1)dow nto 0);beginsig nal o:std_logic_vector(3if start='1' the ndow nto 0);n<="000"beginelse if n="000" the nprocess(clk)if keycode 1="00001"the nvariable num:integer range 0 tofirst<=1;99;elsif keycode 1="00010"

45、the nvariable ten,one: in teger range 0first<=2;to 15;elsif keycode仁"00011"then first<=3;beginelsif keycode仁"00100"then first<=4;if risin g_edge(clk) the nelsif keycode仁"OO1O1"then first<=5;num :=c onv_in teger(keyvalueelsif keycode仁"00110"then fir

46、st<=6;in);elsif keycode仁"00111"then first<=7;if num=0 the nelsif keycode仁"01000"then first<=8;ten:=0;on e:=10;elsif keycode仁"O1OO1"then first<=9;elsif num <10 and num>0elsif keycode 仁"00000" the nthe n ten:=0;one:=num;first<=0;elsif num &l

47、t;20 and num>9end if;the n ten:=1; one:=nu m-10;n<=n+'1'elsif num <30 and num >19elsif n="001"thenthe n ten:=2; one:=nu m-20;ifkeycode 仁"01010"thenelsif num<40 and num >29ysfh<=0;the n ten:=3; one:=nu m-30;elsif keycode 1="01011"the nelsif n

48、um <50 and num >39ysfh<=1;the n ten:=4;one:=num-40;elsif keycode 1="01100"the nelsif num <60 and num >49ysfh<=2;the n ten:=5; one:=nu m-50;end if;elsif num <70 and num >59n<=n+'1'the n ten:=6; one:=nu m-60;elsif n="010"thenelsif num <80 and n

49、um >69if keycode 1="00001"thenthe n ten:=7; one:=nu m-70;second<=1;elsif num <90 and num >79elsif keycode仁"OOO1O"the nthe n ten:=8; one:=nu m-80;second<=2;elsif num<100 and num>89elsif keycode仁"OOO11"the nthe n ten:=9; one:=nu m-90;sec on d<=3;en

50、d if;elsif keycode仁"OO1OO"the nt<=c on v_stdo gic_vector(te n,4);second<=4;elsif keycode 1="00101"theno<=c on v_std_logic_vect or(on e,4)sec on d<=5;elsif keycode仁"OO11O"the ncase t issecond<=6;whe nelsif keycode仁"OO111"the n"0000"=>

51、;show1<="0000000"sec on d<=7;whe nelsif keycode仁"O1OOO"the n"0001"=>show1<="0110000"sec on d<=8;whe nelsif keycode 1="01001"then"0010"=>show1<="1101101"sec on d<=9;whe nelsif keycode仁"OOOOO"the n&

52、quot;0011"=>show1<="1111001"sec on d<=0;whe nend if;"0100"=>show1<="0110011"n<=n+'1'whe nelsif n="011" and keycode仁"01101""0101"=>show1<="1011011"the n ifysfh=0 the nwhe nresult<=first+sec o

53、nd;"0110"=>show1<="0011111"elsif ysfh=1 the n result<=first-whe nsecond;"0111"=>show1<="1110000"elsif ysfh=2 the nwhe nresult<=first*sec ond;"1000"=>show1<="1111111"end if; n<=n+'1'whe nelsif n="100&q

54、uot; the n"1001"=>show1<="1110011"n<="000"whe nend if;others=>show1<="0000000"end if;end case;end process;case o isprocess (n)whe nbegin"0000"=>show2<="1111110"if n="001"the nwhe nkeyvaluei n<=con v_stdo gi

55、c_vector(first,8)"0001"=>show2<="0110000"whe nelsif n="011"then"0010"=>show2<="1101101"keyvalue in<=con v_std_logic_vector(sec onwhe nd,8); elsif n="100"then"0011"=>show2<="1111001"keyvaluei n<=co

56、n v_std _lo gic_vector(result.whe n8);"0100"=>show2<="0110011"end if;whe nend process;"0101"=>show2<="1011011"end Behavioral;whe n"0110"=>show2<="0011111"whe n"0111"=>show2<="1110000"whe n"10

57、00"=>show2<="1111111"whe n "1001"=>show2<="1110011" whe n others=>show2<="0000000" end case;end if;end process;end shumagua nxia nshi ;动态显示：键盘:library IEEE;library IEEE;useuse IEEE.STD_LOGIC_1164.ALL;IEEE.STD_LOGIC_1164.all;use IEEE.STD_

58、LOGIC_ARITH.ALL;useuse IEEE.STD_LOGIC_UNSIGNED.ALL;IEEE.STD_LOGIC_UNSIGNen tity keyboard isED.ALL;Port ( clr: in std_logic;useclk : in STD_LOGIC;ieee. nu meric_std.all;keyin : in STD_LOGIC_VECTOR (3 dow ntoen tity0);shaomiaoxia nshi iskeydrv1:out std_logic_vector(3 dow nto 0);port(clk,clr:inkeyvalue

59、 :outSTD_LOGIC_VECTOR(4std_logic;dow nto 0);show1:i nstart:out stdo gic);stdo gic_vector(6end keyboard;dow nto 0);architecture RTL of keyboard isshow2:i ncomp onent keysca nstdo gic_vector(6Port ( clkin ,clr: inSTD_LOGIC;dow nto 0);keydrv : outSTD_LOGIC_VECTOR(3showout:outdow nto 0);stdo gic_vector(

60、6end comp onent;dow nto 0);comp onent keydecoderen: outPort ( clkin,clk,clr:in std_logic;std_logic_vector(7keyi n : inSTD_LOGIC_VECTOR (3 dow ntodow nto 0);0);endkeycode : outSTD_LOGIC_VECTOR (4shaomiaoxia nshi;dow nto 0);architectureend comp onent;shaomiaoxia nshi ofcomp onent fan gdoushaomiaoxia n

61、shi isport(keycode:i n std_logic_vector(4 dow ntosig nal0);coun t:std_logic_vector(1keycode1:out std_logic_vector(4 dow ntodow nto 0);0);beginsta rt:out std_logic;process(clk)clk_f,clr:i n std_logic);beginend comp onent;if clr='1' thencomp onent frediv ncou nt<="OO"gen eric( n:i nteger:=3);elsePort ( clk in:in STD_LOGIC;if clk'eve nt andclkout:out STD_LOGIC);clk='1' the nend comp onent;if cou nt="