基于FPGA的相位差测量模块的设计

1、精选优质文档-倾情为你奉上基于FPGA的相位差测量模块的设计相位差测量设计思路相位差测量设计要求 基于FPGA设计一个测量两路同频率信号相位差的模块，具体要求如下： 测量信号频率范围： 20Hz20kHz ，精度：2度，测量波形： 方波。自行设计相位差可控双路输出脉冲源作为被测对象。发挥部分：（1）相位差和频率交替显示或同时显示（2）提高测量精度（3）拓宽频率范围到20Hz200kHz（4）设计出一套相位计前置整形电路方案（采用模拟电路或者模数混合，仅设计和仿真，不制作），要求能自适应峰峰值在0.2V至5伏的非方波输入信号，尽量减少两路输入信号幅度不一致引入的误差，带宽不小于20Hz20kHz

2、，输出信号能接入本课题设计的相位差测量模块。相位差测量设计方案根据题目要求，我们组把这个模块的设计分为四个子模块，分别为：信号源的发生、频率计的设计、相位差的测量和四位LED相位差显示。信号源的发生产生两路同频、相位差可控的信号；频率计的设计是借用信号源产生的信号，然后根据内部晶振产生闸门宽度为1秒的闸门信号，在高电平时开始计数，记得的周期个数，即信号源产生信号的频率；相位差的测量是先通过测量两路信号的上升沿之间内部晶振的周期数，然后由此周期数换算出相位差，再通过VHDL语言内部函数转换成十进制数输出到显示模块。RTL图如下：模块程序LIBRARY IEEE;USE IEEE.STD_LOGI

3、C_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY kzys IS PORT ( CLK : IN STD_LOGIC; KG : IN STD_LOGIC; ZS : IN NATURAL; KG_OUT: OUT STD_LOGIC );END entity kzys;ARCHITECTURE one OF kzys ISSIGNAL CNT: NATURAL;BEGIN PROCESS(KG,CLK) BEGIN IF KG='0' THEN CNT<=0; KG_OUT<='0' ELSIF C

4、LK'EVENT AND CLK='1' THEN IF CNT<ZS THEN CNT<=CNT+1; ELSE KG_OUT<='1' END IF; END IF; END PROCESS;END; library ieee;use ieee.std_logic_1164.all;entity xhk isport(sw_1:in std_logic_vector(4 downto 0); f_out1:out natural; y_out2:out natural );end xhk;architecture one of xh

5、k is beginprocess(sw_1)begincase sw_1 iswhen "00001"=>f_out1<=; y_out2<=;when "00010"=>f_out1<=; y_out2<=;when "00011"=>f_out1<=; y_out2<=;when "00100"=>f_out1<=6666; y_out2<=5556;when "00101"=>f_out1<=6666;

6、y_out2<=11111;when "00110"=>f_out1<=6666; y_out2<=16667;when "00111"=>f_out1<=499; y_out2<=1806;when "01000"=>f_out1<=499; y_out2<=1667;when "01001"=>f_out1<=499; y_out2<=625;when "01010"=>f_out1<=82; y_ou

7、t2<=174;when "01011"=>f_out1<=82; y_out2<=81;when "01100"=>f_out1<=82; y_out2<=220;when "01101"=>f_out1<=49; y_out2<=32;when "01110"=>f_out1<=49; y_out2<=65;when "01111"=>f_out1<=49; y_out2<=122;when &q

8、uot;10000"=>f_out1<=0; y_out2<=0;when others=>f_out1<=0; y_out2<=0;end case;end process;end;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY plfsq IS PORT ( clk: IN STD_LOGIC; ZS: IN NATURAL; KG: IN STD_LOGIC; F_OUT : OUT STD_LOGIC );END ;ARCHITE

9、CTURE one OF plfsq ISSIGNAL FULL: STD_LOGIC ;BEGIN PROCESS(clk)VARIABLE CNT8 : NATURAL;BEGIN IF KG='0' THEN FULL <='0' CNT8 :=ZS; ELSIF clk'EVENT AND clk='1' THEN IF CNT8 >0 THEN CNT8:=CNT8-1; ELSE CNT8 :=ZS; FULL <= NOT FULL; END IF; END IF; END PROCESS ;PROCESS

10、(clk,FULL)BEGIN IF KG='1' THEN IF clk 'EVENT AND clk = '1' THEN IF FULL = '1' THEN F_OUT <='1' ELSE F_OUT <='0' END IF; END IF;END IF;END PROCESS;END one; LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY plfsqy IS PORT

11、( clk: IN STD_LOGIC; ZS: IN NATURAL; KG: IN STD_LOGIC; F_OUTY : OUT STD_LOGIC );END ;ARCHITECTURE one OF plfsqy ISSIGNAL FULL: STD_LOGIC ;BEGIN PROCESS(clk)VARIABLE CNT8 : NATURAL;BEGIN IF KG='0' THEN FULL <='0' CNT8 :=ZS; ELSIF clk'EVENT AND clk='1' THEN IF CNT8 >0

12、 THEN CNT8:=CNT8-1; ELSE CNT8 :=ZS; FULL <= NOT FULL; END IF; END IF; END PROCESS ;PROCESS(clk,FULL)BEGIN IF KG='1' THEN IF clk 'EVENT AND clk = '1' THEN IF FULL = '1' THEN F_OUTY <='1' ELSE F_OUTY <='0' END IF; END IF;END IF;END PROCESS;END one;

13、信号源的发生：library ieee;use ieee.std_logic_1164.all;entity xhy isport(sw_1:in std_logic_vector(4 downto 0); clk:in std_logic; kg:in std_logic; f_outy:out std_logic; f_out:out std_logic);end xhy;architecture qq of xhy iscomponent xhkport(sw_1:in std_logic_vector(4 downto 0); f_out1:out natural; y_out2:ou

14、t natural );end component ;component kzys PORT ( CLK : IN STD_LOGIC; KG : IN STD_LOGIC; ZS : IN NATURAL; KG_OUT: OUT STD_LOGIC ); end component;component plfsqy PORT ( clk: IN STD_LOGIC; ZS: IN NATURAL; KG: IN STD_LOGIC; F_OUTY : OUT STD_LOGIC );end component;component plfsq PORT ( clk: IN STD_LOGIC

15、; ZS: IN NATURAL; KG: IN STD_LOGIC; F_OUT : OUT STD_LOGIC ); end component;signal a,b:NATURAL;signal c:STD_LOGIC;beginu1:xhk port map( sw_1=>sw_1,f_out1=>a,y_out2=>b);u2:kzys port map(zs=>b,clk=>clk,kg=>kg,kg_out=>c);u3: plfsqy port map(clk=>clk,ZS=>a, KG=>C,F_OUTY=>

16、F_OUTY);u4: plfsq port map(clk=>clk,ZS=>a,KG=>KG,F_OUT=>F_OUT);END ARCHITECTURE qq;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt10 is port(clk,en,clr:in std_logic; count10:buffer integer range 0 to );end cnt10;architecture art of cnt10 is begin proce

17、ss(clk,clr,en) begin if clr='1'then count10<=0; elsif rising_edge(clk)then if(en='1')then count10<=count10+1; end if; end if; end process; end art;频率计的设计：use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity freq_measure is Port( clk0 : in std_logic; wave1 : in st

18、d_logic; q : out integer range 0 to );end freq_measure;architecture art of freq_measure iscomponent cnt10 port(clk,en,clr:in std_logic; count10:buffer integer range 0 to );end component;signal en1,clr1 : std_logic;signal date:integer range 0 to ;begin process(clk0) variable cnt:integer range 0 to 6;

19、 begin if rising_edge(clk0) then if cnt = 0 then clr1 <= '1'cnt:=1; elsif cnt > 5 then cnt := 0;q<=date; else cnt := cnt+1;clr1 <= '0'en1 <= '1' end if; end if; end process; u1 : cnt10 port map(clk=>wave1,en=>en1,clr=>clr1,count10=>date);end art;lib

20、rary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity measure_n isPort(clk,clk0,clk1:in std_logic; n_out:out std_logic_vector(15 downto 0);end measure_n;architecture art of measure_n issignal count0,count01,count02,count1,count2 : std_logic_vector(

21、15 downto 0);signal x,y,a,clk10,clk11,clk20,clk21: std_logic;beginprocess(clk,clk0,clk1,x,y,count1,count2)beginif clk'event and clk='1'then case a iswhen '0'=>clk10<=clk0;clk11<=clk1; if clk10='0' and clk11='0'then count1<=(others=>'0'); end

22、 if; if clk10='0'then x<='1' end if; if x='1' then if clk10='1' then if clk11='0' then y<='1'end if;if y='1' then if clk11='1' then count01<=count1; count1<=count1;elsecount1<=count1+1; end if; end if; end if;end if;if co

23、unt01=0 thena<='1'else a<='0'end if;when '1'=> clk20<=clk1; clk21<=clk0; if clk20='0' and clk21='0'then count2<=(others=>'0'); end if; if clk20='0'then x<='1' end if; if x='1' then if clk20='1' th

24、en if clk21='0' then y<='1' end if; if y='1' then if clk21='1' then count02<=count2; count2<=count2; else count2<=count2+1; end if; end if; end if; end if; if count02=0 then a<='0' else a<='1'end if;when others=>a<='1' e

25、nd case; count0<=count01 or count02;end if;n_out<=count0;end process;end art;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity consider1 isport ( clk :in std_logic; n1:in std_logic_vector(15 downto 0); freq:in integer range 0 to ; cout

26、:out std_logic_vector(15 downto 0) ); end consider1; architecture arch of consider1 is signal c0,c1,e,e0,d0,d1:integer range 0 to ; signal count:std_logic_vector(15 downto 0); signal m:std_logic_vector(15 downto 0); begin process(n1,clk) begin if rising_edge(clk) then m<=n1; c0<=conv_integer(m

27、); d0<=c0*151; d1<=d0/1024; end if; end process; process(clk,freq) begin if rising_edge(clk) then c1<=freq; e<=c1*d1; e0<=e/2048; count<=conv_std_logic_vector(e0,16); end if; end process; cout<=count; end arch;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL

28、;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity count isport( clk:in std_logic; c_in:in std_logic_vector(15 downto 0);qa1,qb1,qc1,qd1:out INTEGER RANGE 0 TO 9);End count;architecture art of count isSignal a:integer range 0 to ; signal m: std_logic_vector(15 downto 0);BeginProcess(clk,c_in)variable ai,bi,ci,

29、di:integer range 0 to 9;beginif clk'event and clk='1' then m<=c_in;a<=conv_integer(m);di:=(a-ai-10*bi-100*ci) /1000;ci:= (a-ai-10*bi)/100;bi:= (a-ai) rem 100)/10;ai:=a rem 10;end if;qd1<=di;qc1<=ci;qb1<=bi;qa1<=ai;end process;end art;相位差的测量：library IEEE;use IEEE.STD_LOG

30、IC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity phase_measure1 is port( clkin,clk0in,clk1in:in std_logic; qa1out,qb1out,qc1out,qd1out:out integer range 0 to 9 ); end;architecture art of phase_measure1 iscomponent measure_n Port(clk,clk0,clk1:in std_logic; n_out:out st

31、d_logic_vector(15 downto 0);end component;COMPONENT freq_measure Port( clk0 : in std_logic; wave1 : in std_logic; q : out integer range 0 to );end COMPONENT; component consider1 port ( clk :in std_logic; n1:in std_logic_vector(15 downto 0); freq:in integer range 0 to ; cout:out std_logic_vector(15 d

32、ownto 0); end component ;component count port( clk:in std_logic; c_in:in std_logic_vector(15 downto 0); qa1,qb1,qc1,qd1:out integer range 0 to 9);end component;signal d,f: std_logic_vector(15 downto 0);signal e: integer range 0 to ;beginu1: measure_n port map(clk=>clkin,clk0=>clk0in,clk1=>clk1in,n_out=>d);u2: freq_measure port map(clk0=>clkin,wave1=>clk0in,q=>e);u3: consider1 port map(clk=>clkin,n1=>d,freq=>8192,cout=>f);u4: count port map(clk=>clkin,c_in=>f,qa1=>qa1out,qb1=>qb1out,qc1=>qc1out,qd1=>qd1out);end art;四位LE