用状态机实现的EDA多功能数字钟课程设计VHDL代码

1、设计并实现具有一定功能的数字钟1、该数字钟可以实现 3个功能:计时功能、整点报时功能和重置时间功能,因此有 3个功 能:计时、重置时间、复位。2、对所有设计的小系统能够正确分析;3、基于 VHDL 语言描述系统的功能;4、在 quartus 2环境中编译通过;5、仿真通过并得到正确的波形;6、给出相应的设计报告。其中计时模块有 4部分构成:秒计时器(second 、分计时器 (minute、时计时器 (hour、日 计时器 (date、月计时器(mouth 、年计时器(year 1 秒计时器(second 是由一个 60进制的计数器构成的,具有清 0、置数和计数功 能。 其中 reset 为清

2、 0信号, 当 reset 为 0时, 秒计时器清 0; set 为置数信号, 当 set 为 0时, 秒计时器置数,置 s1的值。 clk 为驱动秒计时器的时钟, sec 为秒计时器的输出, ensec 为秒 计时器的进位信号,作为下一级的时钟输入信号。2 分计时器 (minute 是由一个 60进制的计数器构成的, 具有清 0、 置数和计数功能。 其中 reset 为清 0信号,当 reset 为 0时,分计时器清 0; set 为置数信号,当 set 为 0时,分 计时器置数,置 m1的值。 clkm 为驱动分计时器工作的时钟,与 ensec 相连接; min 为分 计时器的输出; en

3、min 为分计时器的进位信号,作为下一级的时钟输入信号。3时计时器(hour 是由一个 24进制的计数器构成的,具有清 0、置数和计数功能。其中 reset 为清 0信号,当 reset 为 0时,时计时器清 0; set 为置数信号,当 set 为 0时,时计时 器置数,置 h1的值。 clkh 为驱动时计时器工作的时钟,与 enmin 相连接; hour 为时计时 器的输出; enhour 为时计时器的进位信号,作为下一级的时钟输入信号。4日计时器(date1是由一个 60进制的计数器构成的,具有清 0、置数和计数功能。其 中 reset 为清 0信号,当 reset 为 0时,星期计时器

4、清 0; set 为置数信号,当 set 为 0时,星 期计时器置数,置 d1的值。 clkd 为驱动星期计时器工作的时钟,与 enhour 相连接; date 为日计时器的输出, endate 为分计时器的进位信号,作为下一级的时钟输入信号,由于月份 的天数存在天数不同,闰年 2月的天数为 28天等情况,还设计了一个润年判别器,准确显 示时间。5月计时器(mouth 是由一个 60进制的计数器构成的,具有清 0、置数和计数功能。其 中 reset 为清 0信号,当 reset 为 0时,星期计时器清 0; set 为置数信号,当 set 为 0时,星 期计时器置数,置 mou1的值, clk

5、mou 为驱动星期计时器工作的时钟,与 enday 相连接; mou 为日计时器的输出, enmou 为分计时器的进位信号,作为下一级的时钟输入信号。 6 计时器 (year 是由一个 60进制的计数器构成的, 具有清 0、 置数和计数功能。 其中 reset 为清 0信号,当 reset 为 0时,星期计时器清 0; set 为置数信号,当 set 为 0时,星期计时 器置数,置 y1的值, clky 为驱动星期计时器工作的时钟,与 enmou 相连接; year 为日计时 器的输出。VHDL 程序1、屏幕切换模块运用状态机进行屏幕切换,分别显示年月日,以及时分秒library IEEE;-

6、 Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;entity mux3 isPort ( clk,Reset,sel : in std_logic;int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12:INSTD_LOGIC_VECTOR(3 DOWNTO 0;- rst musta1,a2,a3,a4

7、,a5,a6: out std_logic_vector(3 downto 0;end mux3;architecture Behavioral of mux3 isTYPE states IS (st0, st1, st2, st3, st4, st5, st6, st7;SIGNAL STX: states ;beginCOM1 : PROCESS(STX,int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12 BEGIN -决定转换状态的进程CASE STX ISWHEN st0 => a1<=int1;a

8、2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6; WHEN st1 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12; WHEN st2 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12; WHEN st3 => a1<=int7;a2<=int8;a3<=int9;a4<=

9、int10;a5<=int11;a6<=int12; WHEN st4 => a1<=int7;a2<=int8;a3<=int9;a4<=int10;a5<=int11;a6<=int12; WHEN st5 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6; WHEN st6 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6;

10、WHEN st7 => a1<=int1;a2<=int2;a3<=int3;a4<=int4;a5<=int5;a6<=int6; WHEN OTHERS => NULL;END CASE ;END PROCESS COM1;REG: PROCESS (clk,Reset,sel -主控时序进程BEGINIF Reset = '1' THEN STX<= st0; -异步复位ELSIF clk='1' AND clk'EVENT THENif sel='1' thenCASE STX

11、 ISWHEN st0=>STX<=st1;WHEN st1=>STX<=st2;WHEN st2=>STX<=st3;WHEN st3=>STX<=st4;WHEN st4=>STX<=st5;WHEN st5=>STX<=st6;WHEN st6=>STX<=st7;WHEN st7=>STX<=st0;END CASE;END IF;END if;END PROCESS;2、显示切换程序library IEEE;- Uncomment the following lines to use th

12、e declarations that are - provided for instantiating Xilinx primitive components. -library UNISIM;entity mux1 isPort ( clk,ina,inb,sel,Reset : in std_logic;result : out std_logic;end mux1;architecture Behavioral of mux1 isTYPE state IS(st0,st1,st2,st3,st4,st5,st6,st7;SIGNAL STX:state;beginREG1: PROC

13、ESS(ina,inb,STXBEGINCASE STX ISWHEN st0=>result<=ina;WHEN st1=>result<=ina;WHEN st2=>result<=inb;WHEN st3=>result<=inb;WHEN st4=>result<=inb;WHEN st5=>result<=inb;WHEN st6=>result<=inb;WHEN st7=>result<=inb;END CASE;END PROCESS;REG2:PROCESS(clk,sel,Res

14、etBEGINIF(Reset='1' THENSTX<=st0;ELSIF(clk'EVENT AND clk='1'THENif sel='1' thenCASE STX ISWHEN st0=>STX<=st1;WHEN st1=>STX<=st2;WHEN st2=>STX<=st3;WHEN st3=>STX<=st4;WHEN st4=>STX<=st5;WHEN st5=>STX<=st6;WHEN st6=>STX<=st7;WHEN

15、 st7=>STX<=st0;END CASE;END IF;end if;END PROCESS REG2;end Behavioral;3、置数操作模块运用状态机,进行置数操作library IEEE;- Uncomment the following lines to use the declarations that are - provided for instantiating Xilinx primitive components. -library UNISIM;entity mux isPort ( clk,ina,inb,sel,Reset : in std_l

16、ogic;r1,r2,r3,r4,r5,r6 : out std_logic;end mux;architecture Behavioral of mux isTYPE state IS(st0,st1,st2,st3,st4,st5,st6,st7;SIGNAL STX:state;beginPROCESS(ina,inb,STXBEGINCASE STX ISWHEN st0=>r1<=ina;r2<='0'r3<='0'r4<='0'r5<='0'r6<='0' WH

17、EN st1=>r1<=ina;r2<='0'r3<='0'r4<='0'r5<='0'r6<='0' WHEN st2=>r1<='0'r2<='0'r3<='0'r4<='0'r5<='0'r6<=inb;WHEN st3=>r1<='0'r2<='0'r3<='0'r4<

18、='0'r5<=inb;r6<='0' WHEN st4=>r1<='0'r2<='0'r3<='0'r4<=inb;r5<='0'r6<='0' WHEN st5=>r1<='0'r2<='0'r3<=inb;r4<='0'r5<='0'r6<='0' WHEN st6=>r1<='0&#

19、39;r2<=inb;r3<='0'r4<='0'r5<='0'r6<='0' WHEN st7=>r1<=inb;r2<='0'r3<='0'r4<='0'r5<='0'r6<='0' END CASE;END PROCESS;PROCESS(clk,sel,ResetBEGINIF(Reset='1' THENSTX<=st0;ELSIF(clk'

20、EVENT AND clk='1'THENif sel='1' thenCASE STX ISWHEN st0=>STX<=st1;WHEN st1=>STX<=st2;WHEN st2=>STX<=st3;WHEN st3=>STX<=st4;WHEN st4=>STX<=st5;WHEN st5=>STX<=st6;WHEN st6=>STX<=st7;WHEN st7=>STX<=st0;END CASE;END IF;end if;END PROCESS;en

21、d Behavioral;end Behavioral;4、秒显示模块library IEEE;- Uncomment the following lines to use the declarations that are - provided for instantiating Xilinx primitive components. -library UNISIM;entity secute1 isPort ( clkm,set,reset : in std_logic;sec2,sec1 : inout std_logic_vector(3 downto 0;ensec : out s

22、td_logic;end secute1;architecture Behavioral of secute1 isbeginProcess(clkm,reset,setBeginIf reset='1' then sec2<="0000"sec1<="0000"Elsif set='1' then sec2<="0101"sec1<="1000"Elsif (clkm'event and clkm='1' thenif sec2=&q

23、uot;0101" AND sec1="1001" then sec2<="0000"sec1<="0000"ensec<='1' elsif sec1="1001" then sec2<=sec2+'1'sec1<="0000"ensec<='0'else sec1<=sec1+'1'ensec<='0'end if;end if;End process;e

24、nd Behavioral;5、分显示模块library IEEE;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;entity minute1 isPort ( clkm,set,reset : in std_logic;min2,min1 : inout std_logic_vector(3 downto 0;enmin : out std_logic;end min

25、ute1;architecture Behavioral of minute1 isbeginProcess(clkm,reset,setBeginIf reset='1' then min2<="0000"min1<="0000"Elsif set='1' then min2<="0101"min1<="1000"Elsif (clkm'event and clkm='1' thenif min2="0101" A

26、ND min1="1001" then min2<="0000"min1<="0000"enmin<='1' elsif min1="1001" then min2<=min2+'1'min1<="0000"enmin<='0'else min1<=min1+'1'enmin<='0'end if;end if;End process;end Behavioral;6、

27、小时显示模块library IEEE;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;entity hour1 isPort ( clkh,set,reset: in std_logic;hor2,hor1 : inout std_logic_vector(3 downto 0;enhour : out std_logic;end hour1;architecture B

28、ehavioral of hour1 isbeginProcess(clkh,reset,setBeginIf reset='1' then hor2<="0000"hor1<="0000"Elsif set='1' then hor2<="0010"hor1<="0011"Elsif (clkh'event and clkh='1' thenif hor2="0010" AND hor1="0011&qu

29、ot; then hor2<="0000"hor1<="0000"enhour<='1' elsif hor1="1001" then hor2<=hor2+'1'hor1<="0000"enhour<='0'else hor1<=hor1+'1'enhour<='0'end if;end if;End process;end Behavioral;7、日显示模块(已加入闰年判断功能lib

30、rary IEEE;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;entity date1 isPort ( clkd,set : in std_logic;dat2,dat1 : inout std_logic_vector(3 downto 0;endate : out std_logic;end date1;architecture Behavioral of d

31、ate1 isbeginProcess(clkd,setBeginif set='1' then dat2<="0010"dat1<="1000"Elsif (clkd'event and clkd='1'thenif dat2="0011" AND dat1="0000" then dat2<="0000"dat1<="0001"endate<='1' elsif dat1="1

32、001" then dat2<=dat2+'1'dat1<="0000"endate<='0'else dat1<=dat1+'1' endate<='0'end if;end if;End process;end Behavioral;8、月显示模块library IEEE;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx

33、 primitive components.-library UNISIM;entity month1 isPort ( clkn,set: in std_logic;mon2,mon1 : inout std_logic_vector(3 downto 0;enmon : out std_logic;end month1;architecture Behavioral of month1 isbeginProcess(clkn,setBeginif set='1' then mon2<="0000"mon1<="0110"Elsif (clkn'event and clkn=