EDA程序改错题

1、程序改错题1.已知 q 均为sel 为 STD_LOGIC_VECTOR(1 DOWNTO 0)STD_LOGIC 类型的信号，请判断下面给出的类型的信号，而a、 b、c、d、CASE 语句程序片段：CASE sel ISWHEN“ 00” =>q<=a；WHEN“ 01” =>q<=b；WHEN“ 10” =>q<=c；WHEN“ 11” =>q<=d；END CASE；答案： CASE 语句缺“ WHEN OTHERS” 语句。2.已知 data_in1, data_in2为 STD_LOGIC_VECTOR(15 DOWNTO 0) 类型的

2、输入端口， data_out为 STD_LOGIC_VECTOR(15 DOWNTO 0) 类型的输出端口，add_sub为 STD_LOGIC 类型的输入端口，请判断下面给出的程序片段：LIBRARY IEEE ；USE IEEE.STD_LOGIC_1164.ALL ；ENTITY add ISPORT（ data_in1, data_in2： IN INTEGER ；data_out：OUT INTEGER ）；END add；ARCHTECTURE add_arch OF add ISCONSTANT a:INTEGER<=2 ；BEGINdata_out<=( data_

3、in1+ data_in2) * a；END addsub_arch；答案：常量声明时赋初值的“<=”符号应改用“ := ”符号。3.已知 Q 为 STD_LOGIC 类型的输出端口，请判断下面的程序片段：ARCHITECTURE test_arch OF test ISBEGINSIGNAL B ：STD_LOGIC ；Q<= B；END test_arch答案：信号 SIGNAL 的声明语句应该放在BEGIN 语句之前。4.已知 A 和 Q 均为 BIT 类型的信号，请判断下面的程序片段：ARCHITECTURE archtest OF test ISBEGINCASE A I

4、SWHEN 0 =>Q<=；1WHEN 1 =>Q<=；0END CASE；END archtest；答案： CASE 语句应该存在于进程PROCESS内。三判断改错题（3 分× 6 题）（评分标准：给出正确答案1 分 /题；答案基本正确0.5 分 /题。）1 已知 A 和 Q 均为 BIT 类型的信号，请判断下面的程序片断：ARCHITECTURE test OF test ISBEGINCASE A ISWHEN '0' => Q <= '1'；WHEN '1' => Q <= 

5、9;0'；END CASE；END test；【参考答案】：CASE 语句应该存在于进程PROCESS 内。2 已知 start 为 STD_LOGIC类型的信号， sum 是 INTEGER 类型的信号，请判断下面的程序片断：PROCESS (start)BEGINFOR i IN 1 TO 9 LOOPsum := sum + i；END LOOP；END PROCESS；【参考答案】：sum 是信号，其赋值符号应该由“:=”改为“ <=”。3 已知 Q 为 STD_LOGIC 类型的输出端口，请判断下面的程序片断：ARCHITECTURE test OF test ISBE

6、GINSIGNAL B：STD_LOGIC；Q<=B；END test；【参考答案】：信号 SIGNAL 的申明语句应该放在BEGIN 语句之前。4 已知 A 和 B 均为 STD_LOGIC 类型的信号，请判断下面的语句：A<='0'；B <= 'x'；【参考答案】：不定态符号应该由小写的x改为大写的X 。5 已知 A 为 INTEGER 类型的信号， B 为 STD_LOGIC 类型的信号，请判断下面的程序片断：ARCHITECTURE test OF test ISBEGINB<=A ；END test；【参考答案】：A 和B的数据

7、类型不一致，不能相互赋值。6 已知 sel 是STD_LOGIC_VECTOR(1 DOWNTO类型0)信号，而 a、b、c、d、q均为 STD_LOGIC类型信号，请判断下面给出的CASE语句：CASE sel ISWHEN“00”WHEN“01”WHEN“10”WHEN“11”=> q <= a => q <= b => q <= c => q <= d；END CASE；【参考答案】：CASE语句缺“ WHEN OTHERS”语句。四、判断下面程序中是否有错误，若有错误请改正；1、SIGNAL A,EN:STD_LOGIC;PROCESS(

8、A,EN)VARIABLE B:STD_LOGIC;BEGINIF EN=1 THENB<=A;END ;END PROCESS;2、RCHITECTURE ONE OF SAMPLE ISVARIABLE A，B，C：INTEGER；BEGINC<=A+B；END ;五、判断下列程序是否有错误，如有则指出错误所在（10 分）程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY zyt12 ISPORT(R,EN,

9、CP:INbit;Q: BUFFER STD_LOGIC_VECTOR(0 DOWNTO 3);CO: OUTSTD_LOGIC);END zyt;ARCHITECTURE c10 OF zyt12BEGINCO<='1' WHEN(EN='1' AND Q="1011") ELSE；'0'PROCESS(R,CP)BEGINIF R='1' THENQ<="0000"ELSIF (CP'EVENT AND CP<='1') THENIF EN=&#

10、39;0' THENQ<=Q;ELSIF Q="1011" THENQ<= 0000 ;ELSEQ:=Q+1;END IF;END PROCESS;END one;仔细阅读下列程序，回答问题LIBRARY IEEE;- 1USE IEEE.STD_LOGIC_1164.ALL;- 2ENTITY LED7SEG IS- 3PORT (A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);- 4CLK: IN STD_LOGIC;- 5LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);- 6END LED7S

11、EG;- 7ARCHITECTURE one OF LED7SEG IS- 8SIGNAL TMP : STD_LOGIC;- 9BEGIN- 10SYNC : PROCESS(CLK, A)- 11BEGIN- 12IF CLK'EVENT AND CLK = '1' THEN- 13TMP <= A;- 14END IF;- 15END PROCESS;- 16OUTLED : PROCESS(TMP)- 17BEGIN- 18CASE TMP IS- 19WHEN "0000" => LED7S <= "011111

12、1"- 20WHEN "0001" => LED7S <= "0000110"- 21WHEN "0010" => LED7S <= "1011011"- 22WHEN "0011" => LED7S <= "1001111"- 23WHEN "0100" => LED7S <= "1100110"- 24WHEN "0101" => LED7S <

13、;= "1101101"- 25WHEN "0110" => LED7S <= "1111101"- 26WHEN "0111" => LED7S <= "0000111"- 27WHEN "1000" => LED7S <= "1111111"- 28WHEN "1001" => LED7S <= "1101111"- 29END CASE;- 30END PROCE

14、SS;- 31END one;- 321. 在程序中存在两处错误，试指出，并说明理由：第 14 行 TMP 附值错误第 29 与 30 行之间，缺少 WHEN OTHERS 语句2. 修改相应行的程序：错误 1行号： 9程序改为：TMP : STD_LOGIC_VECTOR(3 DOWNTO 0);错误 2行号： 29程序改为：该语句后添加WHEN OTHERS => LED7S <= "00000001、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4

15、B ISPORT (CLK，RST， ENA: IN STD_LOGIC;OUTY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT : OUT STD_LOGIC );END CNT4B;ARCHITECTURE behav OF CNT4B ISSIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK, RST, ENA)BEGINIF RST = '1' THEN CQI <= '0000'ELSIF CLK'EVENT AND CLK = '1

16、' THENIF ENA = "1" THEN CQI <= CQI + 1;ELSE CQI <= "0000"END IF;OUTY <= CQI ;"0000"'1'END IF;END PROCESS;COUT<=CQI(0) AND CQI(1) AND CQI(2) AND CQI(3);END behav;2、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_

17、LOGIC_UNSIGNED.ALL;ENTITY CLK_6D ISPORT (CLK,RST: IN STD_LOGIC;CLK_OUT: OUT STD_LOGIC);END CLK_6D;ARCHITECTURE ONE OF CLK_6D ISVARIABLE TEMP:STD_LOGIC;SIGNALBEGINPROCESS(CLK)VARIABLE CNT6D: INTEGER RANGE 0 TO 3;CONSTANT SIGN: INTEGER:=2;BEGINIF (RST =“1” ) THEN TEMP <= “0” ;'1' , '0&#

18、39;ELSIF CLK'EVENT AND CLK='1' THEN(CLK'EVENT AND CLK='1')IF (CNT6D = SIGN) THENCNT6D := 0;TEMP <= NOT TEMP;ELSE CNT6D := CNT6D+1;END IF;END IF;END PROCESS;CLK_OUT <= TEMP;END ONE;3、library ieee;use ieee.std_logic_1164.all;entity encoder isport(b:in std_logic(7downto 0)

19、; b:instd_logic_vector(7downto 0)y: out std_logic(2 downto 0);end encoder;architecture one of encoder isbeginy:out std_logic_vector(2 downto 0)process(b)when others => null;end case;end process;end one;4、 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY counter ISPORT ( reset: IN STD_LOGIC;clock:

20、IN STD_LOGIC;num: buffer integer range 0 to 3 ； 多一个“； ” );END;ARCHITECTURE behav OF jishu IS jishu改为 counterBeginProcess(reset,clock)BeginIf reset=1 thennum<=0;Elsif rising_edge(clock) thenIf num=3 thennum<=0;elsenum<=num+1;少 end if;end if;end process;end;5、 LIBRARY IEEE;USE IEEE.STD_LOGIC_

21、1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED;STD_LOGIC_UNSIGNED.ALLENTITY LX3_2 ISPORT(CLK,CLR,OE:IN BIT;D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END LX3_2;ARCHITECTURE struc OF LX3_2 ISVARIABLE Q_TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNALBEGINPROCESS(CLR)PROCESS(CLK)BEGINIF CLR='0' THEN Q_TEMP<='00000000'"00000000"ELSIF CLK='1' THENQ_TEMP<=D;ELSE Q_TEMP<=Q_TEMP;END I