专用集成电路

1、实验一 EDA软件实验一、实验目的：1、掌握Xilinx ISE 9.2的VHDL输入方法、原理图文件输入和元件库的调用方法。2、掌握Xilinx ISE 9.2软件元件的生成方法和调用方法、编译、功能仿真和时序仿真。3、掌握Xilinx ISE 9.2原理图设计、管脚分配、综合与实现、数据流下载方法。二、实验器材：计算机、Quartus II软件或xilinx ISE三、实验内容：1、 本实验以三线八线译码器（LS74138）为例，在Xilinx ISE 9.2软件平台上完成设计电路的VHDL文本输入、语法检查、编译、仿真、管脚分配和编程下载等操作。下载芯片选择Xilinx公司的CoolRu

2、nner II系列XC2C256-7PQ208作为目标仿真芯片。2、 用1中所设计的的三线八线译码器（LS74138）生成一个LS74138元件，在Xilinx ISE 9.2软件原理图设计平台上完成LS74138元件的调用，用原理图的方法设计三线八线译码器（LS74138），实现编译，仿真，管脚分配和编程下载等操作。四、实验步骤：1、三线八线译码器（LS 74138）VHDL电路设计(1)三线八线译码器（LS74138）的VHDL源程序的输入打开Xilinx ISE 6.2编程环境软件Project Navigator，执行“file”菜单中的【New Project】命令，为三线八线译码器

3、（LS74138）建立设计项目。项目名称【Project Name】为“Shiyan”,工程建立路径为“C:XilinxbinShiyan1”，其中“顶层模块类型（Top-Level Module Type）”为硬件描述语言（HDL），如图1所示。图1点击【下一步】，弹出【Select the Device and Design Flow for the Project】对话框，在该对话框内进行硬件芯片选择与工程设计工具配置过程。图2完成具体选择后点击【下一步】弹出如图3所示对话框，在该对话框内创建文件资源。图3图4打开【New Source】标签，弹出如图4所示对话框在【File】 

4、;标签下对话框内写入用户自定义的文件名称，标签【Locatior】下显示了新定义文件的创建路径，选中标签【Add to proje】前的对号标记，将新创建的文件74ls138添加到工程 “Shiyan”中。点击【下一步】，弹出如图5所示对话框，在此对话框中输入三线八线译码器（LS 74138）的的端口信息。图5点击【下一步】弹出【New Source Information】对话框，在该对话框内显示了新建文件的属性及信息，如图6所示。图6点击【完成】标签结束新建工程过程。进入Xilinx ISE文本编辑方式，在文本框中编辑输入3线8线译码器的VHDL源程序。library IEEE;use I

5、EEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity ls74138 is Port ( G1 : in std_logic;G2 : in

6、std_logic;INP : in std_logic_vector(2 downto 0); Y : out std_logic_vector(7 downto 0);end ls74138;architecture Behavioral of ls74138 isbeginprocess(G1,G2,INP)begin if(G1 and G2)='1') thencase INP is when "000"=>Y<="00000001" when "001"=>Y<="0000

7、0010" when "010"=>Y<="00000100"when "011"=>Y<="00001000"when "100"=>Y<="00010000" when "101"=>Y<="00100000"when "110"=>Y<="01000000" when "111"=>Y<=&

8、quot;10000000"when others=>Y<="00000000" end case;elseY<="00000000"end if;end process;end Behavioral;在VHDL源程序中，G1和G2为两个使能控制信号，INP为命令码输入信号，Y为8位译码输出信号。（2）、设计文件存盘与语法检查完成程序代码输入后单击高亮“ls74138-behavioral”标签，此时工具窗口将显示 “Process for Source(ls74138-behavioral)”。用鼠标右键点击Process窗

9、口中【Check Syntax】标签，点击运行选项，进行程序语法检查，当显示一绿色对号标志时即表示程序中不存在语法问题。或双击【Synthesize-XST】当显示一绿色对号标志时即表示程序综合成功。（3）、仿真文件设计为了验证所设计电路功能，需要输入测试文件对电路程序功能进行测试。在【Process】菜单中选择【New Source】选项，即可弹出对话框，选择【VHDL Test Bench】添加测试向量文件，并将文件添加到LS74138模块中运行行为仿真选项卡【Behavioral Simulation】，在测试向量文件中填写代码，完成后保存，Xilinx ISE自动调用ModelSim

10、SE 6.1c仿真平台作为仿真工具。运行ModelSim SE 6.1c，。在【transcript】窗口中输入仿真时间。在波形【Wave】窗口内使用按钮实现仿真图的“放大”“缩小”“全局”功能，由图中时序及逻辑关系可知该三线八线译码器行为仿真正常。图11测试向量参考程序如下：- VHDL Test Bench Created from source file ls74138.vhd - - Notes: - This testbench has been automatically generated using types std_logic and- std_logic_vector f

11、or the ports of the unit under test. Xilinx recommends - that these types always be used for the top-level I/O of a design in order - to guarantee that the testbench will bind correctly to the post-implementation - simulation model.-LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;E

12、NTITY ls74138_ls74138_vhd_tb ISEND ls74138_ls74138_vhd_tb;ARCHITECTURE behavior OF ls74138_ls74138_vhd_tb IS COMPONENT ls74138PORT(G1 : IN std_logic;G2 : IN std_logic;INP : IN std_logic_vector(2 downto 0); Y : OUT std_logic_vector(7 downto 0);END COMPONENT;SIGNAL G1 : std_logic;SIGNAL G2 : std_logic

13、;SIGNAL INP : std_logic_vector(2 downto 0);SIGNAL Y : std_logic_vector(7 downto 0);BEGINuut: ls74138 PORT MAP(G1 => G1,G2 => G2,INP => INP,Y => Y);- * Test Bench - User Defined Section *u1:PROCESS wait for 15 us; BEGININP<="010" G1<='0'wait for 15 us; wait for 15

14、us;INP<="011" G1<='1'wait for 15 us; wait for 100 us;INP<="100" G1<='0'wait for 15 us; wait for 15 us;INP<="101" G1<='1'wait for 15 us; wait;INP<="110" END PROCESS u1;wait for 15 us;u2:PROCESSINP<="111"

15、 BEGINwait for 30 us; G2<='0' INP<="000" wait for 15 us;wait; G2<='1'end PROCESS u3; wait for 100 us;- * End Test Bench - User Defined Section * G2<='0'END behavior ; wait for 15 us; G2<='1' wait; END PROCESS u2;u3:PROCESS BEGIN INP<="

16、000" wait for 30 us; INP<="001"（4）芯片管脚定义如前所述添加用户定义限制文件，运行【Assign Package Pins】选项卡，Xilinx ISE将弹出管脚分配窗口，输入各个端口管脚位置并保存，完成芯片管脚定义。（5）编译与综合图16 图17运行【Process for Source】中的【Implement Design】（图16），ISE将自动完成编译并调用内嵌的综合工具XST完成综合过程，运行结果如图17所示。编译通过后即自动生成了电路烧录下载文件（*.jed）以及资源消耗报告，通过该报告即可了解所设计电路的资源消

17、耗情况。由图可知，在三线八线译码器（74LS138）的设计中使用了8个宏单元，9个乘积项，8个寄存器单元，13个用户引脚及5个功能输入块。2、元件的生成、调用和仿真新建原理图文件，命名为 “Sch_LS74138”并添加到工程“Shiyan”中。点击【下一步】完成原理图文件的创建。在弹出的原理图编辑框内选择【Symbols】标签，在其目录列表内显示了所有可用电路器件，其中包括了我们所设计的LS74138。双击“ls74138”将其放置到原理图编辑区内。点击为器件添加外围端口。将原理图文件保存后返回【Xilinx Project Navigator】平台，此时已经将程序所设计的器件“LS7413

18、8”配置给了原理图文件“sch_ls74138”。实验二 组合逻辑电路的VHDL语言实现一、实验目的：1、掌握VHDL语言设计基本单元及其构成2、掌握用VHDL语言设计基本的组合逻辑电路的方法。二、实验器材：计算机、Quartus II软件或Xilinx ISE三、实验内容：1、以四选一选择器为例，在Xilinx ISE软件平台上完成设计电路的VHDL文本输入，编辑，编译，仿真，管脚分配和编程下载等操作。四、实验步骤：（一）、用VHDL语言实现四选一选择器的设计并实现功能仿真。选择器常用于信号的切换，四选一选择器可以用于4路信号的切换。其真值表如下所示： 表3 四选一真值表选择输入数据输入数据

19、输出baInput0Input1Input2Input3y000xxx0001xxx101x0xx001x1xx110xx0x010xx1x111xxx0011xxx11用VHDL语言实现四选一选择器的设计并实现功能仿真。参考程序如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux4 IS PORT (INPUT:IN STD_LOGIC_VECTOR (3 DOWNTO 0);A,B:IN STD_LOGIC;Y:OUT STD_LOGIC);END mux4;ARCHITECTURE rt1 OF mux4 ISSIGNAL se1:

20、STD_LOGIC_VECTOR (1 DOWNTO 0);BEGIN se1<=B&A; PROCESS (INPUT,se1) BEGIN IF(se1="00")THEN y<=INPUT(0); ELSIF(se1="01")THEN y<=INPUT(1); ELSIF(se1="10")THEN y<=INPUT(2); ELSE y<=INPUT(3); END IF; END PROCESS;END rt1;测试向量程序如下：- VHDL Test Bench Created fr

21、om source file mux4.vhd - Notes: - This testbench has been automatically generated using types std_logic and- std_logic_vector for the ports of the unit under test. Xilinx recommends - that these types always be used for the top-level I/O of a design in order - to guarantee that the testbench will b

22、ind correctly to the post-implementation - simulation model.LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;ENTITY mux4_mux4_vhd_tb ISEND mux4_mux4_vhd_tb;ARCHITECTURE behavior OF mux4_mux4_vhd_tb IS COMPONENT mux4PORT(INPUT : IN std_logic_vector(3 downto 0);A : IN std_logic;B : IN

23、 std_logic; Y : OUT std_logic);END COMPONENT;SIGNAL INPUT : std_logic_vector(3 downto 0);SIGNAL A : std_logic;SIGNAL B : std_logic;SIGNAL Y : std_logic;BEGINuut: mux4 PORT MAP(INPUT => INPUT,A => A,B => B,Y => Y);- * Test Bench - User Defined Section *u1: PROCESS BEGINA<='0' B

24、<='1'wait for 15us;wait for 5 us;A<='1' B<='0'wait for 15us;wait for 5 us;A<='0' B<='1'wait for 5us;wait;A<='1'end process u2;wait for 5 us;u3: processA<='0'beginwait; INPUT<="1101" END PROCESS u1;wait for 10us

25、;u2: process INPUT <="1010" beginwait for 10us;B<='0' INPUT <="0111" wait for 10us;wait for 20us;B<='1' INPUT <="0001" wait for 20us;wait for 10us;B<='0' INPUT<="0010" wait for 5us;wait ; end process u3; - * End Tes

26、t Bench - User Defined Section *END behavior;仿真结果如下图：实验三 时序逻辑电路的VHDL语言实验一、实验目的：1、掌握用VHDL语言设计基本的时序逻辑电路及仿真。2、掌握VHDL顺序语句和并行语句的异同3、掌握触发器同步复位和异步复位的实现方式。4、掌握软件时钟的加入方法。二、实验器材：计算机、Quartus II软件或xilinx ISE三、实验内容：1、设计带使能的递增计数器2、在步骤1的基础上设计一带使能的同步（异步）复位的递增（递减）计数器四、实验步骤：参考程序：library ieee;use ieee.std_logic_1164.a

27、ll;use ieee.std_logic_unsigned.all;entity ycounter is port(clk,clear,ld,enable:in std_logic; d:in std_logic_vector(7 downto 0); qk:out std_logic_vector(7 downto 0);end ycounter;architecture a_ycounter of ycounter isbegin PROCESS (clk) VARIABLE cnt :std_logic_vector(7 downto 0); BEGIN IF (clk'EVE

28、NT AND clk = '1') THEN IF(clear = '0') THEN cnt := "00000000"ELSE IF(ld = '0') THENcnt := d;ELSEIF(enable = '1') THENcnt := cnt + "00000001"END IF; END IF;END IF;END IF;qk <= cnt; END PROCESS;end a_ycounter;测试向量如下：- VHDL Test Bench Created from

29、source file ycounter.vhd - 16:50:55 03/24/2008- Notes: - This testbench has been automatically generated using types std_logic and- std_logic_vector for the ports of the unit under test. Xilinx recommends - that these types always be used for the top-level I/O of a design in order - to guarantee tha

30、t the testbench will bind correctly to the post-implementation - simulation model.LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;ENTITY ycounter_a_ycounter_vhd_tb ISEND ycounter_a_ycounter_vhd_tb;ARCHITECTURE behavior OF ycounter_a_ycounter_vhd_tb IS COMPONENT ycounterPORT(clk : I

31、N std_logic;clear : IN std_logic;ld : IN std_logic;enable : IN std_logic;d : IN std_logic_vector(7 downto 0); qk : OUT std_logic_vector(7 downto 0);END COMPONENT;constant clk_cycle: time:=20 us;SIGNAL clk : std_logic;SIGNAL clear : std_logic;SIGNAL ld : std_logic;SIGNAL enable : std_logic;SIGNAL d :

32、 std_logic_vector(7 downto 0);SIGNAL qk : std_logic_vector(7 downto 0);BEGINuut: ycounter PORT MAP(clk => clk,clear => clear,ld => ld,enable => enable,d => d,qk => qk);- * Test Bench - User Defined Section *u1 : PROCESSwait for clk_cycle/2; BEGINclk<='1' clk<='0&#

33、39;wait for clk_cycle/2;wait for clk_cycle/2;clk<='0'clk<='1'wait for clk_cycle/2;wait for clk_cycle/2;clk<='1'clk<='0'wait ;wait for clk_cycle/2;END PROCESS u1;clk<='1'u2: processwait for clk_cycle/2;beginclk<='0'clear<='0'

34、;wait for clk_cycle/2;wait for clk_cycle;clk<='1'clear<='1'wait for clk_cycle/2;wait;clk<='0'end process;wait for clk_cycle/2;u3: processclk<='1'beginwait for clk_cycle/2;ld<='1'clk<='0'wait for clk_cycle*6;wait for clk_cycle/2;ld<

35、='0'clk<='1'wait ;wait for clk_cycle/2;end process u3;clk<='0'u4: processwait for clk_cycle/2;beginclk<='1'enable<='1'wait for clk_cycle/2;wait ;clk<='0'end process u4;u5: process begin d<="00001111" wait; end process u5; -

36、* End Test Bench - User Defined Section *END behavior;仿真结果如图所示：实验四 VHDL层次化设计方法实验一、实验目的：1、掌握用VHDL语言层次化设计的基本方法。2、掌握GENERATE语句的用法。二、实验器材：计算机、Quartus II软件或xilinx ISE三、实验内容：设计一8位异步计数器，它的上一位计数器的输出作为下一位计数器的时钟信号，一级一级串行连接构成一个异步计数器。各个D触发器模块采用VHDL语言编写，分别用原理图和VHDL语言元件例化语句的方法实现8位异步计数器的设计。四、实验步骤：（一）、在原理图中调用VHDL生成

37、的D触发器模块实现8位异步计数器的设计 1、在xilinx ISE环境中新建vhdl文本编辑文件，设计带清零端的D触发器并编译仿真。 2、将步骤1所设计的D触发器生成一个元件。3、新建原理图文件，调用步骤2所生成的D触发器元件，在原理图中实现8位异步计数器。（二）、用VHDL的COMPONENT语句调用VHDL生成的D触发器模块实现8位异步计数器设计。 1、在xilinx ISE环境中新建vhdl文本编辑文件，设计带清零端的D触发器并编译仿真。2、在同一个程序中用COMPONENT语句实现8位异步计数器的设计。library IEEE;use IEEE.STD_LOGIC_1164.ALL;u

38、se IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity dff isport ( d,clk,clear: in std_logic; q,q_n: out std_logic );end d

39、ff;architecture Behavioral of dff isbeginprocess(clk,clear)beginif (clear='0') then q<='0'elsif(clk'event and clk='1') then q<=d; q_n<=not d;end if;end process;end Behavioral;D触发器测试向量程序如下：Test Bench Created from source file dff.vhd - - Notes: - This testbench has

40、 been automatically generated using types std_logic and- std_logic_vector for the ports of the unit under test. Xilinx recommends - that these types always be used for the top-level I/O of a design in order - to guarantee that the testbench will bind correctly to the post-implementation - simulation

41、 model.-LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;ENTITY dff_dff_vhd_tb ISEND dff_dff_vhd_tb;ARCHITECTURE behavior OF dff_dff_vhd_tb IS COMPONENT dffPORT(d : IN std_logic;clear: in std_logic;clk : IN std_logic; q : OUT std_logic;q_n: out std_logic);END COMPONENT;SIGNAL d : st

42、d_logic;signal clear: std_logic;SIGNAL clk : std_logic;SIGNAL q : std_logic;signal q_n: std_logic;BEGINuut: dff PORT MAP(d => d,clear=>clear,clk => clk,q => q,q_n=> q_n);u1: PROCESS BEGINclk<='0'wait for 5us;clk<='1'wait for 5us;clk<='0'wait for 5us;cl

43、k<='1'wait for 5us;clk<='0'wait for 5us;clk<='1'wait for 5us;clk<='0'wait for 5us;clk<='1'wait for 5us;clk<='0'wait for 5us;clk<='1'wait;end process u1;u2: processbegind<='0'wait for 15us;d<='1' wait f

44、or 25us; d<='0' wait ;end process u2;u3: processbeginclear<='1' wait for 35us;clear<='0'wait for 10us; clear<='1' wait ; end process u3; - * End Test Bench - User Defined Section *END behavior;程序仿真如下图：新建原理图文件，调用步骤1所生成的D触发器元件，在原理图中实现8位异步计数器：end Behavioral;L

45、IBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY rplcont ISPORT(clk,clr:in std_logic; count:out std_logic_vector(7 downto 0);END rplcont;ARCHITECTURE rtl OF rplcont ISsignal count_in_bar:std_logic_vector(8 downto 0);component dffrport(clk,clr,d:in std_logic; q,qb:out std_logic);end component;begincoun

46、t_in_bar(0)<=clk;gen1:for i in 0 to 7 generateu:dffr port map(clk=>count_in_bar(i),clr=>clr,d=>count_in_bar(i+1),q=>count(i),qb=>count_in_bar(i+1);end generate;end rtl;（三） 测试向量设计Test Bench Created from source file dff.vhd - - Notes: - This testbench has been automatically generated using types std_logic and- std_logic_vector for the ports of the unit under test. Xilinx recommends - that these types always be used for the top-level I/O of a design in order - to guarantee that the testbench will bind correctly to the post-implementation - simulation model.-LIBRAR