FPGA蓝牙控制电子琴

1、深圳大学考试答题纸（以论文、报告等形式考核专用） 二。一二O 五学年度第学期课程编课程名主讲教评,02数字系统设计XXXX号称师分学号XXXX姓名 XXX专业年级XXXXX教师评语:题目：蓝牙控制电子发生器摘要：基于Basys2设计平台而搭建的“谱曲软件在 fpga上的实现”的系统，融入了蓝牙传输模 块，VGA显示模块，以及安卓手机的 app应用软件，完成了对课题的基本功能的实现。谱曲软件由我校陈必红老师编写，通过输入“陈谱”，实现了对钢琴曲以及一般的乐曲的播放，软件界面如下在界面的最下部分编写陈谱，再点击装入，就会出现美妙的乐曲1、系统总流程1.1系统总框图1.2系3统总框图介绍1.33设计

2、中遇至V的难点、舍弃。2、蓝牙模块1.1 蓝 牙 模 块 波 特 率 设 置 以 及信号测 ASM1.2ASM5,63、A模块（VGA莫块由周玲同学编写实现）4、分频器模块4.1ASM利用及布局-9过程中遇到的难点以星舍弃；H不得不说，这个设计只是当初设憩的半成晶，为什么这么说呢？亠赛必红老师所绸写的谱曲软伴冃的是完全模拟钢琴的波形，述就必镰要有一FD丸转换模块” 而Dm转换模块有两种“ 一种是以PCF8591芯片为例子的12C总线控制的F 一种是以,DAC0832为 例子的T型解码网络的*"笔者前明使用的是DAC0832 片，在开题后的一个星期内*笔者利用单片机幵发，经过上几十次

3、的实验，发现DAC0832输出效果菲常不理炬，出现的扁差菲常大，在找资糾，验证芯片的时候耗 费了大部分的时间*后来了笔者找到了 PCF08J2：利用单片机进行测试后效果基本能够接爱，但 展*由于I2C总线实现的困难以及时间上的问題，笔者最终放弃了 DA转换，改用最基本的分频器 模块，十分遗憾。我波特率设置模块以及检波else日cn t<=c nt+1'b1;always (posedge clk or posedge rst_ n) beg inclk_bps_r<=1'b1;输出0elseclk_bps_r<=1'b0;endassig n clk_

4、bps = clk_bps_r;en dmoduleinput clk;input rst_n;input rs232_rx; /input clk_bps;output bps_start;output 7:0 rx_data;output rx_int; output 9:0 led;output reg7:0 led_new;reg 9:0 led;reg rs232_rx0,rs232_rx1,rs232_rx2,rs232_rx3;wire neg_rs232_rx;always (posedge clk or posedge rst_n) beginif(rst_n) beginr

5、s232_rx0 <= 1'b0;rs232_rx1 <= 1'b0;rs232_rx2 <= 1'b0;rs232_rx3 <= 1'b0;endelse beginrs232_rx0 <= rs232_rx;rs232_rx1 <= rs232_rx0;rs232_rx2 <= rs232_rx1;rs232_rx3 <= rs232_rx2;endendassign neg_rs232_rx = rs232_rx3 & rs232_rx2 &rs232_rx1 &rs232_rx0;

6、reg bps_start_r;reg 3:0 num;reg rx_int;always (posedge clk or posedge rst_n)if(rst_n) beginbps_start_r <=1'bz;rx_int <= 1'b0;endelse if(neg_rs232_rx) begin/ bps_start_r <= 1'b1; * _ rx_int <= 1'b1;endelse if(num=4'd12) beginbps_start_r <=1'b0;rx_int <= 1'

7、;b0;end从蓝牙模块（硬件）处接收到下沿标志启动信号检测模块（即上assign bps_start = bps_start_r;reg 7:0 rx_data_r;reg 7:0 rx_temp_data;always (posedge clk or posedge rst_n) if(rst_n) beginled<=10'b000_0000000; rx_temp_data <= 8'd0; num <= 4'd0; rx_data_r <= 8'd0;endelse if(rx_int) begin if(clk_bps) be

8、gin num <= num+1'b1; case(num)4'd1: rx_temp_data0 <= rs232_rx;4'd2: rx_temp_data1 <= rs232_rx;4'd3: rx_temp_data2 <= rs232_rx;4'd4: rx_temp_data3 <= rs232_rx;4'd5: rx_temp_data4 <= rs232_rx;4'd6: rx_temp_data5 <= rs232_rx;4'd7: rx_temp_data6 <=

9、 rs232_rx;4'd8: rx_temp_data7 <= rs232_rx; default:;endcase case(rx_temp_data) 8'b00000000:led<=10'b000_0000000; 8'b00000001:led<=10'b001_0000001;8'b00000010:led<=10'b001_0000010;检测后得到汁£分八次检测，分别存入8位的寄存器编码（10位）：输出Vga不编码：输8'b00000011:led<=10'b001

10、_0000100;8'b00000100:led<=10'b001_0001000;8'b00000101:led<=10'b001_0010000;8'b00000110:led<=10'b001_0100000;8'b00000111:led<=10'b001_1000000;8'b00001000:led<=10'b010_0000001;8'b00001001:led<=10'b010_0000010;8'b00001010:led<=10&

11、#39;b010_0000100;8'b00001011:led<=10'b010_0001000;8'b00001100:led<=10'b010_0010000;8'b00001101:led<=10'b010_0100000;8'b00001110:led<=10'b010_1000000;8'b00001111:led<=10'b100_0000001;8'b00010000:led<=10'b100_0000010;8'b00010001:led

12、<=10'b100_0000100;8'b00010010:led<=10'b100_0001000;8'b00010011:led<=10'b100_0010000;8'b00010100:led<=10'b100_0100000;8'b00010101:led<=10'b100_1000000; endcase led_new<=rx_temp_data;endelse if(num=4'd12) beginnum <= 4'd0; /数据接收完毕rx_data

13、_r<=rx_temp_data;endendassign rx_data = rx_data_r;endmodulemodule sound(clk,rst_n,led_new,sound_out);input clk;in注意：ed_Sw为调试初期是使用led来进行检测的，某些命名不方便改output reg sound_out;fre；Vaii®此就继续沿用always(posedge clk or posedge rst_n) begin if(isl n)value<= 1'b0;else begin case(led_new) 8'd1:fre

14、<=18'd18898; 8'd2:fre<=18'd21212; 8'd3:fre<=18'd19515; 8'd4:fre<=18'd25223; 8'd5:fre<=18'd28315; 8'd6:fre<=18'd31783; 8'd7:fre<=18'd35674; 8'd8:fre<=18'd37796; 8'd9:fre<=18'd42424; 8'd10:fre<=18'

15、;d47588; 8'd11:fre<=18'd50451; 8'd12:fre<=18'd56608; 8'd13:fre<=18'd63566; 8'd14:fre<=18'd71348; 8'd15:fre<=18'd75592; 8'd16:fre<=18'd84843; 8'd17:fre<=18'd95177; 8'd18:fre<=18'd100846; 8'd19:fre<=18'd

16、113259; 8'd20:fre<=18'd127130; 8'd21:fre<=18'd142680; default:fre<=18'd86; endcase value <= value +fre; end end接收到蓝牙主模块发送过来的8位信号，并if(value < 32'h7FFF_FFFF)sound_out <= 1'b0;elsesound_out <= 1'b1;endend endmoduleFPGA开发的布局布线后的时序和资源利用报告 实验成功的开发板截图 最终

17、主模块代码 module tonetop(clk,clr,rxd,hsync,vsync,rgb_8bits,sound_out);input clk;input clr;input rxd;output hsync;output vsync;output 7:0 rgb_8bits;output sound_out;wire 7:0 led_new;wire9:0 control;wire 20:0 tone;sound s(.clk(clk),.rst_n(clr),.led_new(led_new),.sound_out(sound_out);uart_top uut4(.clk(clk

18、),.rst_n(clr),.rs232_rx(rxd),.led(control),.led_new(led_new);keyna uut1(.clr(clr),.clk(clk),.control(control),.tone(tone);vga uut2(.clk(clk),.clr(clr),.tone(tone),.hsync(hsync),.vsync(vsync),.rgb_8bits(rgb_8bits);Endmodule分频器代码module sound(clk,rst_n,led_new,sound_out);input clk;input rst_n;input 7:0

19、 led_new;output reg sound_out;reg 18:0 fre;/parameter FREQ_WORD = 32'd44; /1KHzreg 31:0 value=0;always(posedge clk or posedge rst_n)beginif(rst_n)value<= 1'b0;elsebegincase(led_new)8'd1:fre<=18'd18898;8'd2:fre<=18'd21212;8'd3:fre<=18'd19515;8'd4:fre<

20、;=18'd25223;8'd5:fre<=18'd28315;8'd6:fre<=18'd31783;8'd7:fre<=18'd35674;8'd8:fre<=18'd37796;8'd9:fre<=18'd42424;8'd10:fre<=18'd47588;8'd11:fre<=18'd50451;8'd12:fre<=18'd56608;8'd13:fre<=18'd63566;8

21、'd14:fre<=18'd71348;8'd15:fre<=18'd75592;8'd16:fre<=18'd84843;8'd17:fre<=18'd95177;8'd18:fre<=18'd100846;8'd19:fre<=18'd113259;8'd20:fre<=18'd127130;8'd21:fre<=18'd142680;default:fre<=18'd86;endcasevalue &

22、lt;= value +fre;endend/always(posedge clk or posedge rst_n)beginif(rst_n)sound_out<= 1'b0;elsebeginif(value < 32'h7FFF_FFFF)sound_out <= 1'b0;elsesound_out <= 1'b1;endendendmodule蓝牙主模块代码'timescale 1ns/1psmodule uart_top(clk,rst_n,rs232_rx,led,led_new);input clk; / 时钟信

23、号 50Minput rst_n; / 复位信号 , 低有效input rs232_rx; / 数据输入信号 / 数据输出信号output 9:0 led;output 7:0 led_new;wire 7:0 led_new;wire bps_start1,bps_start2;/wire clk_bps1,clk_bps2;wire 7:0 rx_data; /接收数据存储器 ,用来存储接收到的数据 , 直到下一个数据接收wire rx_int; /接收数据中断信号 , 接收过程中一直为高 ,/ 子模块端口申明 / speed_select_rx speed_rx( /数据接收波特率选择模

24、块.clk(clk),.rst_n(rst_n),.bps_start(bps_start1),.clk_bps(clk_bps1);uart_rx uart_rx( /数据接收模块.clk(clk),.rst_n(rst_n),.bps_start(bps_start1),.clk_bps(clk_bps1),.rs232_rx(rs232_rx),.rx_data(rx_data),.rx_int(rx_int),.led(led),.led_new(led_new);Endmodule波特率设置以及信号检测代码module speed_select_rx(clk,rst_n,bps_st

25、art,clk_bps);/input clk; /50M input rst_n; / input bps_start; /时钟复位信号接收到信号以后,波特率时钟信号置位波特率设定,当接收到 uart_rx 传来的信号以后 , 模块开始运行output clk_bps; /接收数据中间采样点/ 'define BPS_PARA 5207;/9600 波特率分频计数值 / 'define BPS_PARA_2 2603;/ 计数一半时采样 reg12:0 cnt;/分频计数器reg clk_bps_r;/波特率时钟寄存器reg2:0 uart_ctrl;/波特率选择寄存器alw

26、ays (posedge clk or posedge rst_n)if(rst_n)cnt<=13'd0;else if(cnt=5207)| !bps_start)/判断计数是否达到 1 个脉宽cnt<=13'd0;elsecnt<=cnt+1'b1;/ 波特率时钟启动always (posedge clk or posedge rst_n) beginif(rst_n) clk_bps_r<=1'b0;else if(cnt= 2603)/ 当波特率计数到一半时 , 进行采样存储 clk_bps_r<=1'b1;els

27、eclk_bps_r<=1'b0;将采样数据输出给 uart_rx 模块endassign clk_bps = clk_bps_r;/ endmodule蓝牙数据接收以及编码代码module uart_rx(clk,rst_n, bps_start, clk_bps, rs232_rx, rx_data, rx_int, led,led_new);input clk; / 时钟input rst_n; / input rs232_rx; / input clk_bps; / output bps_start; /复位接收数据信号高电平时为接收信号中间采样点接收信号时 , 波特率时

28、钟信号置位output 7:0 rx_data;/接收数据寄存器output rx_int; / 接收数据中断信号 , 接收过程中为高output 9:0 led;output reg7:0 led_new;接收数据寄存器reg 9:0 led;reg rs232_rx0,rs232_rx1,rs232_rx2,rs232_rx3;/ wire neg_rs232_rx;/ 表示数据线接收到下沿 always (posedge clk or posedge rst_n) begin if(rst_n) beginrs232_rx0 <= 1'b0;rs232_rx1 <=

29、1'b0;rs232_rx2 <= 1'b0;rs232_rx3 <= 1'b0;end else beginrs232_rx0 <= rs232_rx;rs232_rx1 <= rs232_rx0; rs232_rx2 <= rs232_rx1; rs232_rx3 <= rs232_rx2; end串口传输线的下沿标志endassign neg_rs232_rx = rs232_rx3 & rs232_rx2 & rs232_rx1 & rs232_rx0;/ reg bps_start_r;reg 3:0

30、 num;/ 移位次数reg rx_int; / 接收中断信号 always (posedge clk or posedge rst_n) if(rst_n) begin bps_start_r <=1'bz;rx_int <= 1'b0; endelse if(neg_rs232_rx) begin/ bps_start_r <= 1'b1; / 启动串口 , 准备接收数据 rx_int <= 1'b1; / 接收数据中断使能 endelse if(num=4'd12) begin /接收完有用的信号 ,bps_start_r

31、<=1'b0; / 接收完毕 , 改变波特率置位 , 方便下次接收 rx_int <= 1'b0; / 接收信号关闭 end assign bps_start = bps_start_r;reg 7:0 rx_data_r;/ 串口数据寄存器 reg 7:0 rx_temp_data;/ 当前数据寄存器 always (posedge clk or posedge rst_n) if(rst_n) beginled<=10'b000_0000000; rx_temp_data <= 8'd0; num <= 4'd0;rx_

32、data_r <= 8'd0;endelse if(rx_int) begin /接收数据处理if(clk_bps) beginnum <= num+1'b1;case(num)4'd1: rx_temp_data0 <= rs232_rx;4'd2: rx_temp_data1 <= rs232_rx;4'd3: rx_temp_data2 <= rs232_rx;4'd4: rx_temp_data3 <= rs232_rx;4'd5: rx_temp_data4 <= rs232_rx;4&

33、#39;d6: rx_temp_data5 <= rs232_rx;4'd7: rx_temp_data6 <= rs232_rx;4'd8: rx_temp_data7 <= rs232_rx; default: ;endcasecase(rx_temp_data)8'b00000000:led<=10'b000_0000000;8'b00000001:led<=10'b001_0000001;8'b00000010:led<=10'b001_0000010;8'b00000011:l

34、ed<=10'b001_0000100;8'b00000100:led<=10'b001_0001000;8'b00000101:led<=10'b001_0010000;8'b00000110:led<=10'b001_0100000;8'b00000111:led<=10'b001_1000000;8'b00001000:led<=10'b010_0000001;8'b00001001:led<=10'b010_0000010;8'b00

35、001010:led<=10'b010_0000100;8'b00001011:led<=10'b010_0001000;8'b00001100:led<=10'b010_0010000;8'b00001101:led<=10'b010_0100000;8'b00001110:led<=10'b010_1000000;8'b00001111:led<=10'b100_0000001;8'b00010000:led<=10'b100_0000010;8

36、'b00010001:led<=10'b100_0000100;8'b00010010:led<=10'b100_0001000;8'b00010011:led<=10'b100_0010000;8'b00010100:led<=10'b100_0100000;8'b00010101:led<=10'b100_1000000;endcase led_new<=rx_temp_data;endelse if(num=4'd12) beginnum <= 4'd

37、0; / 数据接收完毕 rx_data_r<=rx_temp_data;endendassign rx_data = rx_data_r;endmoduleVGA数据接收以及编码代码module keyna(control,clr,clk,tone);input 9:0 control;input clk;input clr;output reg 20:0 tone;always (posedge clk or posedge clr)if(clr=1'b1)tone<=21'd0;elsebegincase(control9:7)3'b100:beginc

38、ase(control6:0)7'b1000000:tone<=21'b1_0000_0000_0000_0000_0000;7'b0100000:tone<=21'b0_1000_0000_0000_0000_0000;7'b0010000:tone<=21'b0_0100_0000_0000_0000_0000;7'b0001000:tone<=21'b0_0010_0000_0000_0000_0000;7'b0000100:tone<=21'b0_0001_0000_0000_

39、0000_0000;7'b0000010:tone<=21'b0_0000_1000_0000_0000_0000;7'b0000001:tone<=21'b0_0000_0100_0000_0000_0000;endcaseend3'b010:begincase(control6:0)7'b1000000:tone<=21'b0_0000_0010_0000_0000_0000;7'b0100000:tone<=21'b0_0000_0001_0000_0000_0000;7'b00100

40、00:tone<=21'b0_0000_0000_1000_0000_0000;7'b0001000:tone<=21'b0_0000_0000_0100_0000_0000;7'b0000100:tone<=21'b0_0000_0000_0010_0000_0000;7'b0000010:tone<=21'b0_0000_0000_0001_0000_0000;7'b0000001:tone<=21'b0_0000_0000_0000_1000_0000;endcaseend3'b

41、001:begincase(control6:0)7'b1000000:tone<=21'b0_0000_0000_0000_0100_0000;7'b0100000:tone<=21'b0_0000_0000_0000_0010_0000;7'b0010000:tone<=21'b0_0000_0000_0000_0001_0000;7'b0001000:tone<=21'b0_0000_0000_0000_0000_1000;7'b0000100:tone<=21'b0_0000_

42、0000_0000_0000_0100;7'b0000010:tone<=21'b0_0000_0000_0000_0000_0010;7'b0000001:tone<=21'b0_0000_0000_0000_0000_0001;endcaseenddefault:tone<=21'd0;endcaseendendmoduleVGA数据输出代码module vga(clk,clr,hsync,vsync,rgb_8bits,tone);input 20:0 tone;input clk;input clr;output wire hs

43、ync;output wire vsync;output rgb_8bits;reg 7:0 rgb_8bits;reg 10:0 cnt_h;reg 9:0 cnt_v;wire 10:0 count_h;wire 9:0 count_v;assign count_h = cnt_h-150;assign count_v = cnt_v;always(posedge clk or posedge clr)beginif(clr)cnt_h <= 11'd0;else if(cnt_h = 11'd1056)cnt_h <= 11'd0;elsecnt_h

44、<= cnt_h + 1;endalways(posedge clk or posedge clr)if(clr)cnt_v <= 10'd0;else if (cnt_v = 10'd625)cnt_v <= 10'd0;else if (cnt_h = 11'd1056)cnt_v <= cnt_v +1;/*/assign hsync = (cnt_h<=11'd80) ? 1'b0 : 1'b1;assign vsync = (cnt_v<=10'd3) ? 1'b0 : 1&#

45、39;b1;wire a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,a16,a17,a18,a19,a20,a21;assign a1=(count_h>=100 && count_h<=120&& count_v>=100&& count_v<=350)|(count_h>=100&& count_h<=129&& count_v>350&&count_v<=500)&&(ton

46、e0=1'b0)?1'b1:1'b0; assign a2=(count_h>=140 && count_h<=150&&count_v>=100&&count_v<=350)|(count_h>=131&&count_h<=159&&count_v>350&&count_v<=500)&&(tone1=1'b0)?1'b1:1'b0; assign a3=(count_h>=170

47、 && count_h<=189&&count_v>=100&&count_v<=350)|(count_h>=161&&count_h<=189&&count_v>350&&count_v<=500)&&(tone2=1'b0)?1'b1:1'b0; assign a4=(count_h>=191 && count_h<=210&&count_v>=100&&

48、amp;count_v<=350)|(count_h>=191&&count_h<=219&&count_v>350&&count_v<=500)&&(tone3=1'b0)?1'b1:1'b0; assign a5=(count_h>=230 && count_h<=240&&count_v>=100&&count_v<=350)|(count_h>=221&&count_h<

49、=249&&count_v>350&&count_v<=500)&&(tone4=1'b0)?1'b1:1'b0; assign a6=(count_h>=260 && count_h<=270&&count_v>=100&&count_v<=350)|(count_h>=251&&count_h<=279&&count_v>350&&count_v<=500)&

50、;&(tone5=1'b0)?1'b1:1'b0; assign a7=(count_h>=290 && count_h<=309&&count_v>=100&&count_v<=350)|(count_h>=281&&count_h<=309&&count_v>350&&count_v<=500)&&(tone6=1'b0)?1'b1:1'b0; assign a8=(count

51、_h>=311 && count_h<=330&&count_v>=100&&count_v<=350)|(count_h>=311&&count_h<=339&&count_v>350&&count_v<=500)&&(tone7=1'b0)?1'b1:1'b0; assign a9=(count_h>=350 && count_h<=360&&count_v>

52、=100&&count_v<=350)|(count_h>=341&&count_h<=369&&count_v>350&&count_v<=500)&&(tone8=1'b0)?1'b1:1'b0;assign a10=(count_h>=380 && count_h<=399&&count_v>=100&&count_v<=350)|(count_h>=371&&c

53、ount_h<=399&&count_v>350&&count_v<=500)&&(tone9=1'b0)?1'b1:1'b0;assign a11=(count_h>=401 && count_h<=420&&count_v>=100&&count_v<=350)|(count_h>=401&&count_h<=429&&count_v>350&&count_v<

54、;=500)&&(tone10=1'b0)?1'b1:1'b0; assign a12=(count_h>=440 && count_h<=450&&count_v>=100&&count_v<=350)|(count_h>=431&&count_h<=459&&count_v>350&&count_v<=500)&&(tone11=1'b0)?1'b1:1'b0; ass

55、ign a13=(count_h>=470 && count_h<=480&&count_v>=100&&count_v<=350)|(count_h>=461&&count_h<=489&&count_v>350&&count_v<=500)&&(tone12=1'b0)?1'b1:1'b0; assign a14=(count_h>=500 && count_h<=519&&count_v>=100&&count_v<=350)|(count_h>=491&&count_h<=519&&count_v>350&&count_v<=500)&&(tone13=1'b0)?1'b1:1'b0; assign a15=(count_h>=521 && count_h<=540&&count_v>=100&&count_v<=350)|