FPGA实验三：液晶屏的显示设计

1、专业：_电子信息工程_姓名：_陈华杰_学号：_日期：_4月4日_地点：应电楼303桌号2组 实验报告课程名称：_FPGA实验_指导老师：_竺红卫/陈宏_成绩：_实验名称：_液晶屏的显示设计_实验类型：_FPGA实验_同组学生姓名：_一、 实验目的1. 熟悉实验板上液晶屏的工作原理；2. 熟悉驱动电路的源代码。二、实验装置1. 电脑一台；2. 实验板一块；3. 实验板电源一只；4. 实验板连接电脑的下载线一根。三、实验原理实验板显著的特征是2 线16 字符液晶显示器LCD。尽管LCD 支持8 位的数据接口，为了与其它的XILINX 的开发板保持兼容并且尽可能减少针脚数， FPGA 仅通过4 位的

2、数据接口线控制LCD， LCD 通过使用ASCII 标准和自定义字符可以有效地显示多种信息。但是，这些显示速度并不是很快。每半秒扫描一次以测试实际清晰度的界限。与50MHz 时钟频率相比，这样的显示速度是慢的。 PicoBlaze 处理器可以有效地控制显示时间和显示内容。字符 LCD 的供电电压是5V。 FPGA 的I/O 口信号的电压是3.3V。但是， FPGA 的输出电平是通过LCD 来识别是有效的低电平还是高电平。 LCD 控制器接收5V TTL 信号电平， FPGA输出3.3V 的LCMOS 以满足5V TTL 电压要求。数据线上的390 欧串联电阻，当LCD 驱动一个逻辑高电平时，其

3、用来防止了FPGA 和SrtataFlsah I/O 管脚的超负载。当LCD_RW 为高时， LCD驱动数据线。在绝大多数应用中， LCD作为只读外围设备，几乎没有从显示器读数据。四、操作方法和实验步骤对于程序的各个步骤，如新建项目、新建Verilog HDL、新建.ucf文件、Synthesize、Implement Design、Generate Programming File、Configure Target Device等等，在实验一中已经展示过，每一次实验的基本操作步骤都是差不多的，故这里不再重复阐述。本次实验总共需要做三份程序并观察现象：1）例程2）设计按键拨动时显示小时、分钟和

4、秒，中间分别空一格。3）按键拨动开始显示，10秒钟显示结束，结束时LCD上显示ABCDEF，同时八只LED灯亮。五、实验源代码和现象1）例程UCF文件如下：NET "CLK_50MHZ" LOC="C9"NET "LCD_D<0>" LOC="R15"NET "LCD_D<1>" LOC="R16"NET "LCD_D<2>" LOC="P17"NET "LCD_D<3>&quo

5、t; LOC="M15"NET "LCD_E" LOC="M18"NET "LCD_RS" LOC="L18"NET "LCD_RW" LOC="L17"源代码如下：module lcd_write_number_test(input CLK_50MHZ,output LCD_E,output LCD_RS,output LCD_RW,output 3:0 LCD_D);wire if_ready;reg if_write;reg 31:0 if_data

6、;reg 1:0 state;reg 31:0 cntr;parameter IDLE = 2'b00,IF_WRITE_1 = 2'b01,SET_IF_WRITE_0 = 2'b10,WAIT = 2'b11;/ Instantiate the Unit Under Test (UUT)lcd_write_number uut(.CLK_50MHZ(CLK_50MHZ),.LCD_E(LCD_E),.LCD_RS(LCD_RS),.LCD_RW(LCD_RW),.LCD_D(LCD_D),.if_data(if_data),.if_write(if_writ

7、e),.if_ready(if_ready);initial beginif_data <= 32'habba0123;state <= IDLE;if_write <= 1'b0;cntr <= 32'b0;endalways (posedge CLK_50MHZ) begincase (state)IDLE:if (if_ready) beginif_data <= if_data + 1'b1;if_write <= 1'b1;state <= IF_WRITE_1;cntr <= 32'b0

8、;endIF_WRITE_1: / this state to keep if_write up for 2 cyclesstate <= SET_IF_WRITE_0;SET_IF_WRITE_0: / set if_write 0 and start the counterbeginif_write <= 1'b0;state <= WAIT;cntr <= 32'b0;endWAIT:if (cntr < 25000000) / wait for 0.5 secondscntr <= cntr + 32'b1;elsestate

9、 <= IDLE;endcaseendendmoduletimescale 1ns / 1psmodule lcd_write_number(input CLK_50MHZ,output LCD_E,output LCD_RS,output LCD_RW,output 3:0 LCD_D,input 31:0 if_data,input if_write,output if_ready);reg 7:0 disp_data;reg disp_rs;reg 31:0 disp_delay;reg disp_write;wire disp_ready;reg disp_b8;reg 7:0

10、char;reg 1:0 state;reg 31:0 number;reg init_done;reg running;reg 4:0 shift_cntr;reg if_ready_r;assign if_ready = if_ready_r;lcd_display display(.clk(CLK_50MHZ),.rst(1'b0),.lcd_e(LCD_E),.lcd_rw(LCD_RW),.lcd_rs(LCD_RS),.lcd_d(LCD_D),.if_data(disp_data),.if_rs(disp_rs),.if_delay(disp_delay),.if_wri

11、te(disp_write),.if_ready(disp_ready),.if_8bit(disp_b8);parameter NB_CHARS = 8'd12;parameter START = 2'b00,WAIT_WRITE_0 = 2'b01,WRITE_1 = 2'b10,WAIT_WRITE_1 = 2'b11;initial beginstate <= 2'b00;char <= 8'b0;init_done <= 1'b0;if_ready_r <= 1'b0;shift_cntr

12、 <= 5'b0;endalways (posedge CLK_50MHZ) beginif (init_done && char > 8'd16) beginif (disp_ready)if_ready_r <= 1'b1;if (if_write) beginchar <= 4'd8; / reset the displayendend else if (char <= 8'd16) beginif_ready_r <= 1'b0;case (state)START:if (disp_re

13、ady) begindisp_write <= 1'b1;state <= WAIT_WRITE_0;endWAIT_WRITE_0:state <= WRITE_1;WRITE_1:begindisp_write <= 1'b0;state <= 2'b11;endWAIT_WRITE_1:beginstate <=START;char <= char + 8'b1;endendcase / case (state)end / else: !if(!running)end / always (posedge CLK_5

14、0MHZ)always (negedge CLK_50MHZ) begin/ these next steps initialize the LCD display:case (char)0:begindisp_b8 <= 1'b0;disp_data <= 8'h30;disp_delay <= 32'd10000000;disp_rs <= 1'b0;end1: disp_data <= 8'h30;2:begindisp_data <= 8'h30;disp_delay <= 32'd100

15、0000;end3:begindisp_data <= 8'h20;disp_delay <= 32'd20000;end4:begindisp_b8 <= 1'b1;disp_data <= 8'h28;end5: disp_data <= 8'h06;6: disp_data <= 8'h0C;7:begindisp_data <= 8'h01;disp_delay <= 32'd1000000;init_done <= 1'b1;shift_cntr <=

16、5'd9;end8: / this state provides an entry point to reset the display and then/ go on to the default state that writes the numberbegindisp_rs <= 1'b0;disp_data <= 8'h01;disp_delay <= 32'd1000000;shift_cntr <= 5'b0;number <= if_data;enddefault:/ state machine to prin

17、t a 32-bit number outif (disp_ready && state = START) beginif (shift_cntr < 5'd8) begindisp_rs <= 1'b1;disp_delay <= 32'd20000;if (number31:28 < 4'b1010)disp_data <= number31:28 + 8'h30;elsedisp_data <= number31:28 + 8'h37;number <= number <<

18、; 4;shift_cntr <= shift_cntr + 5'b1;endendendcase / case (char)end / always (negedge CLK_50MHZ)endmoduletimescale 1ns / 1psmodule lcd_display(input clk,input rst,output lcd_e,output lcd_rw,output lcd_rs,output 3:0 lcd_d,input 7:0 if_data,input if_rs,input 31:0 if_delay,input if_write,output i

19、f_ready,input if_8bit);reg 2:0 state;reg lcdr_e;reg 3:0 lcdr_d;reg 31:0 wait_cntr;reg ready;reg init_done;parameter IDLE = 3'b000,WAIT_PULSE_E_0 = 3'b001,LOAD_LOWER_NIBBLE = 3'b010,WAIT_PULSE_E_1 = 3'b011,WAIT_COMMAND = 3'b100;parameter PULSE_E_DLY = 32'd12;parameter INIT_TIM

20、E = 32'd20000000;assign lcd_d = lcdr_d;assign lcd_rs = if_rs;assign lcd_rw = 1'b0;assign lcd_e = lcdr_e;assign if_ready = ready;initial beginstate <= IDLE;ready <= 1'b0;lcdr_e <= 1'b0;init_done <= 1'b0;endalways (posedge clk) beginif (rst) beginstate <= IDLE;end el

21、se if (!init_done) beginif (wait_cntr < INIT_TIME)wait_cntr <= wait_cntr + 1;else begininit_done <= 1'b1;ready <= 1'b1;endend else begincase (state)IDLE:beginif (if_write) beginlcdr_e <= 1'b1;lcdr_d <= if_data7:4; / upper nibble firstready <= 1'b0;wait_cntr <=

22、 32'b0;state <= WAIT_PULSE_E_0;endendWAIT_PULSE_E_0:if (wait_cntr < PULSE_E_DLY) beginwait_cntr <= wait_cntr + 1;end else beginlcdr_e <= 1'b0;wait_cntr <= 0;if (if_8bit)state <= LOAD_LOWER_NIBBLE;elsestate <= WAIT_COMMAND;endLOAD_LOWER_NIBBLE:if (wait_cntr < PULSE_E_D

23、LY) beginwait_cntr <= wait_cntr + 1;end else beginwait_cntr <= 0;lcdr_e <= 1'b1;lcdr_d <= if_data3:0; / lower nibblestate <= WAIT_PULSE_E_1;endWAIT_PULSE_E_1:if (wait_cntr < PULSE_E_DLY) beginwait_cntr <= wait_cntr + 1;end else beginlcdr_e <= 1'b0;wait_cntr <= 0;st

24、ate <= WAIT_COMMAND;endWAIT_COMMAND:if (wait_cntr < if_delay) beginwait_cntr <= wait_cntr + 32'b1;end else beginwait_cntr <= 0;if (!if_write) beginstate <= IDLE;ready <= 1'b1;endendendcase / case (state)endendendmodule共有三个module，它们的包含关系为lcd_write_number_test包含lcd_write_numb

25、er，lcd_write_number包含lcd_display，下同。实验现象：如下图，刚烧录程序完时，LCD前8位依次显示十六进制数“ABBA0123”，然后每过0.5秒，该数值增一，满十六进位。2）设计按键拨动时显示小时、分钟和秒，中间分别空一格。UCF文件如下：NET "CLK_50MHZ" LOC="C9"NET "LCD_D<0>" LOC="R15"NET "LCD_D<1>" LOC="R16"NET "LCD_D<2&

26、gt;" LOC="P17"NET "LCD_D<3>" LOC="M15"NET "LCD_E" LOC="M18"NET "LCD_RS" LOC="L18"NET "LCD_RW" LOC="L17"NET "SW1" LOC="L14"源代码如下：module lcd_write_number_test(input SW1,input CLK_50

27、MHZ,output LCD_E,output LCD_RS,output LCD_RW,output 3:0 LCD_D);wire if_ready;reg if_write;reg 31:0 if_data;reg 1:0 state;reg 31:0 cntr;parameter IDLE = 2'b00,IF_WRITE_1 = 2'b01,SET_IF_WRITE_0 = 2'b10,WAIT = 2'b11;/ Instantiate the Unit Under Test (UUT)lcd_write_number uut(.SW1(SW1),.

28、CLK_50MHZ(CLK_50MHZ),.LCD_E(LCD_E),.LCD_RS(LCD_RS),.LCD_RW(LCD_RW),.LCD_D(LCD_D),.if_data(if_data),.if_write(if_write),.if_ready(if_ready);initial beginif_data <= 32'h19044012;state <= IDLE;if_write <= 1'b0;cntr <= 32'b0;endalways (posedge CLK_50MHZ) begincase (state)IDLE:if

29、(if_ready) beginif(if_data31:0=32'h23059059)if_data <= 32'h0;else if(if_data27:0=28'h9059059)if_data <= if_data + 32'h6fa6fa7;else if(if_data19:0=20'h59059)if_data <= if_data + 32'hfa6fa7;else if(if_data15:0=16'h9059)if_data <= if_data + 32'h6fa7;else if(i

30、f_data7:0=8'h59)if_data <= if_data + 32'hfa7;else if(if_data3:0=4'h9)if_data <= if_data + 32'h7;else if_data <= if_data + 1'b1;if_write <= 1'b1;state <= IF_WRITE_1;cntr <= 32'b0;endIF_WRITE_1: / this state to keep if_write up for 2 cyclesstate <= SET_

31、IF_WRITE_0;SET_IF_WRITE_0: / set if_write 0 and start the counterbeginif_write <= 1'b0;state <= WAIT;cntr <= 32'b0;endWAIT:if (cntr < 50000000) / wait for 1 secondscntr <= cntr + 32'b1;elsestate <= IDLE;endcaseendendmoduletimescale 1ns / 1psmodule lcd_display(input clk,

32、input rst,output lcd_e,output lcd_rw,output lcd_rs,output 3:0 lcd_d,input 7:0 if_data,input if_rs,input 31:0 if_delay,input if_write,output if_ready,input if_8bit);reg 2:0 state;reg lcdr_e;reg 3:0 lcdr_d;reg 31:0 wait_cntr;reg ready;reg init_done;parameter IDLE = 3'b000,WAIT_PULSE_E_0 = 3'b0

33、01,LOAD_LOWER_NIBBLE = 3'b010,WAIT_PULSE_E_1 = 3'b011,WAIT_COMMAND = 3'b100;parameter PULSE_E_DLY = 32'd12;parameter INIT_TIME = 32'd20000000;assign lcd_d = lcdr_d;assign lcd_rs = if_rs;assign lcd_rw = 1'b0;assign lcd_e = lcdr_e;assign if_ready = ready;initial beginstate <

34、= IDLE;ready <= 1'b0;lcdr_e <= 1'b0;init_done <= 1'b0;endalways (posedge clk) beginif (rst) beginstate <= IDLE;end else if (!init_done) beginif (wait_cntr < INIT_TIME)wait_cntr <= wait_cntr + 1;else begininit_done <= 1'b1;ready <= 1'b1;endend else begincas

35、e (state)IDLE:beginif (if_write) beginlcdr_e <= 1'b1;lcdr_d <= if_data7:4; / upper nibble firstready <= 1'b0;wait_cntr <= 32'b0;state <= WAIT_PULSE_E_0;endendWAIT_PULSE_E_0:if (wait_cntr < PULSE_E_DLY) beginwait_cntr <= wait_cntr + 1;end else beginlcdr_e <= 1'

36、b0;wait_cntr <= 0;if (if_8bit)state <= LOAD_LOWER_NIBBLE;elsestate <= WAIT_COMMAND;endLOAD_LOWER_NIBBLE:if (wait_cntr < PULSE_E_DLY) beginwait_cntr <= wait_cntr + 1;end else beginwait_cntr <= 0;lcdr_e <= 1'b1;lcdr_d <= if_data3:0; / lower nibblestate <= WAIT_PULSE_E_1;

37、endWAIT_PULSE_E_1:if (wait_cntr < PULSE_E_DLY) beginwait_cntr <= wait_cntr + 1;end else beginlcdr_e <= 1'b0;wait_cntr <= 0;state <= WAIT_COMMAND;endWAIT_COMMAND:if (wait_cntr < if_delay) beginwait_cntr <= wait_cntr + 32'b1;end else beginwait_cntr <= 0;if (!if_write) b

38、eginstate <= IDLE;ready <= 1'b1;endendendcase / case (state)endendendmoduletimescale 1ns / 1psmodule lcd_write_number(input CLK_50MHZ,input SW1,output LCD_E,output LCD_RS,output LCD_RW,output 3:0 LCD_D,input 31:0 if_data,input if_write,output if_ready);reg 7:0 disp_data;reg disp_rs;reg 31:

39、0 disp_delay;reg disp_write;wire disp_ready;reg disp_b8;reg 7:0 char;reg 1:0 state;reg 31:0 number;reg init_done;reg running;reg 4:0 shift_cntr;reg if_ready_r;assign if_ready = if_ready_r;lcd_display display(.clk(CLK_50MHZ),.rst(1'b0),.lcd_e(LCD_E),.lcd_rw(LCD_RW),.lcd_rs(LCD_RS),.lcd_d(LCD_D),.

40、if_data(disp_data),.if_rs(disp_rs),.if_delay(disp_delay),.if_write(disp_write),.if_ready(disp_ready),.if_8bit(disp_b8);parameter NB_CHARS = 8'd12;parameter START = 2'b00, WAIT_WRITE_0 = 2'b01, WRITE_1 = 2'b10, WAIT_WRITE_1 = 2'b11; initial beginstate <= 2'b00;char <= 8&

41、#39;b0;init_done <= 1'b0;if_ready_r <= 1'b0;shift_cntr <= 5'b0;endalways (posedge CLK_50MHZ) beginif (init_done && char > 8'd16) begin if (disp_ready) if_ready_r <= 1'b1; if (if_write) begin char <= 4'd8; / reset the display endend else if (char <

42、= 8'd16) begin if_ready_r <= 1'b0; case (state) START:if (disp_ready) begindisp_write <= 1'b1;state <= WAIT_WRITE_0;endWAIT_WRITE_0:state <= WRITE_1;WRITE_1:begindisp_write <= 1'b0;state <= 2'b11;endWAIT_WRITE_1:beginstate <= START;char <= char + 8'b1;

43、endendcase / case (state)end / else: !if(!running)end / always (posedge CLK_50MHZ)always (negedge CLK_50MHZ) begin/ these next steps initialize the LCD display:case (char)0:begindisp_b8 <= 1'b0;disp_data <= 8'h30;disp_delay <= 32'd10000000;disp_rs <= 1'b0;end1: disp_data

44、<= 8'h30;2:begindisp_data <= 8'h30;disp_delay <= 32'd1000000;end3:begindisp_data <= 8'h20;disp_delay <= 32'd20000;end4:begindisp_b8 <= 1'b1;disp_data <= 8'h28;end5: disp_data <= 8'h06;6: disp_data <= 8'h0C;7:begindisp_data <= 8'h0

45、1;disp_delay <= 32'd1000000;init_done <= 1'b1;shift_cntr <= 5'd9;end8: / this state provides an entry point to reset the display and then/ go on to the default state that writes the numberbegindisp_rs <= 1'b0;disp_data <= 8'h01;disp_delay <= 32'd1000000;shif

46、t_cntr <= 5'b0;number <= if_data;enddefault:/ state machine to print a 32-bit number outif (SW1)beginif (disp_ready && state = START) begin if (shift_cntr < 5'd8) begin disp_rs <= 1'b1; disp_delay <= 32'd20000; if(shift_cntr = 5'd2) | (shift_cntr = 5'd5

47、) begin disp_data <= 8'h20; endelse begin if (number31:28 < 4'b1010) disp_data <= number31:28 + 8'h30; else disp_data <= number31:28 + 8'h37; endnumber <= number << 4; shift_cntr <= shift_cntr + 5'b1;endendendendcase / case (char)end / always (negedge CLK_

48、50MHZ)endmodule实验现象：当SW1为低电平时，LCD无显示。SW1向上拨后，如下图，LCD显示小时、分钟和秒，中间分别空一格，且该输出显示会按照时钟的样式计时、刷新，每过一秒钟秒位进一，秒的个位满10进位，秒数满60则分数增一当SW1再次向下拨，LCD显示关闭，但始终仍然在计时。程序刚烧进板子时，时钟的初始时间是人为设定的19时44分12秒。3）按键拨动开始显示，10秒钟显示结束，结束时LCD上显示ABCDEF，同时八只LED灯亮。UCF文件如下：NET "CLK_50MHZ" LOC="C9"NET "LCD_D<0>

49、;" LOC=R15;NET "LCD_D<1>" LOC=R16;NET "LCD_D<2>" LOC=P17;NET "LCD_D<3>" LOC=M15;NET "LCD_E" LOC=M18;NET "LCD_RS" LOC=L18;NET "LCD_RW" LOC=L17;NET "SW1" LOC=L14;NET "LED0" LOC=F12;NET "LED1&quo

50、t; LOC=E12;NET "LED2" LOC=E11;NET "LED3" LOC=F11;NET "LED4" LOC=C11;NET "LED5" LOC=D11;NET "LED6" LOC=E9;NET "LED7" LOC=F9;源代码如下：module lcd_write_number_test(input CLK_50MHZ,input SW1,output LCD_E,output LCD_RS,output LCD_RW,output 3:0 LCD_

51、D,output LED0,output LED1,output LED2,output LED3,output LED4,output LED5,output LED6,output LED7);wire if_ready;reg if_write;reg 31:0 if_data;reg 1:0 state;reg 31:0 cntr;parameter IDLE = 2'b00,IF_WRITE_1 = 2'b01,SET_IF_WRITE_0 = 2'b10,WAIT = 2'b11;/ Instantiate the Unit Under Test (

52、UUT)lcd_write_number uut(.SW1(SW1),.CLK_50MHZ(CLK_50MHZ),.LCD_E(LCD_E),.LCD_RS(LCD_RS),.LCD_RW(LCD_RW),.LCD_D(LCD_D),.if_data(if_data),.if_write(if_write),.if_ready(if_ready),.LED0(LED0),.LED1(LED1),.LED2(LED2),.LED3(LED3),.LED4(LED4),.LED5(LED5),.LED6(LED6),.LED7(LED7);initial beginif_data <= 32

53、'h19044012;state <= IDLE;if_write <= 1'b0;cntr <= 32'b0;endalways (posedge CLK_50MHZ) begincase (state)IDLE:if (if_ready) beginif(if_data31:0=32'h23059059)if_data <= 32'h0;else if(if_data27:0=28'h9059059)if_data <= if_data + 32'h6fa6fa7;else if(if_data19:0=

54、20'h59059)if_data <= if_data + 32'hfa6fa7;else if(if_data15:0=16'h9059)if_data <= if_data + 32'h6fa7;else if(if_data7:0=8'h59)if_data <= if_data + 32'hfa7;else if(if_data3:0=4'h9)if_data <= if_data + 32'h7;else if_data <= if_data + 1'b1;if_write <

55、;= 1'b1;state <= IF_WRITE_1;cntr <= 32'b0;endIF_WRITE_1: / this state to keep if_write up for 2 cyclesstate <= SET_IF_WRITE_0;SET_IF_WRITE_0: / set if_write 0 and start the counterbeginif_write <= 1'b0;state <= WAIT;cntr <= 32'b0;endWAIT:if (cntr < 50000000) / wa

56、it for 1 secondscntr <= cntr + 32'b1;elsestate <= IDLE;endcaseendendmoduletimescale 1ns / 1psmodule lcd_write_number(input CLK_50MHZ,input SW1,output LCD_E,output LCD_RS,output LCD_RW,output 3:0 LCD_D,output LED0,output LED1,output LED2,output LED3,output LED4,output LED5,output LED6,outpu

57、t LED7,input 31:0 if_data,input if_write,output if_ready);reg 7:0 disp_data;reg disp_rs;reg 31:0 disp_delay;reg disp_write;wire disp_ready;reg disp_b8;reg 7:0 char;reg 1:0 state;reg 31:0 number;reg init_done;reg running;reg 4:0 shift_cntr;reg if_ready_r;reg 28:0 cnt;reg cnt_state;reg light;assign if

58、_ready = if_ready_r;lcd_display display(.clk(CLK_50MHZ),.rst(1'b0),.lcd_e(LCD_E),.lcd_rw(LCD_RW),.lcd_rs(LCD_RS),.lcd_d(LCD_D),.if_data(disp_data),.if_rs(disp_rs),.if_delay(disp_delay),.if_write(disp_write),.if_ready(disp_ready),.if_8bit(disp_b8);parameter NB_CHARS = 8'd12;parameter START =

59、2'b00, WAIT_WRITE_0 = 2'b01, WRITE_1 = 2'b10, WAIT_WRITE_1 = 2'b11; initial beginstate <= 2'b00;char <= 8'b0;init_done <= 1'b0;if_ready_r <= 1'b0;shift_cntr <= 5'b0;cnt_state <= 1'b0;cnt <= 29'b0;light <= 1'b0;endalways (posedge CLK_50MHZ) beginif (init_done && char > 8'd16) begin if (disp_ready) if_ready_r <= 1'b1; if (if_write) begin char <= 4'd8; / reset the display endend else if (char <= 8'd16) begi