移位寄存器设计

1、实验名称 移位寄存器设计一：实验目的二：实验所用仪表及主要器材三：实验原理简述（源程序、真值表、原理图）四：实验测量记录（数据、仿真波形图及分析、源程序分析、硬件测试实时分析）五：实验心得（实验中问题的解决方法等）一：实验目的(1)掌握移位寄存器电路设计的方法。(2)通过开发CPLD来实现时序逻辑电路的功能。二：实验所用仪表及主要器材 Max+plus2软件。三：实验原理简述（源程序、真值表、原理图）（1）环形计数器源程序：library IEEE;use IEEE.std_logic_1164.all;entity huanxing is port ( clk : in std_logic;

2、 load : in std_logic; d : in std_logic_vector(3 downto 0); q : out std_logic_vector(3 downto 0);end entity;architecture shft_reg_arch of huanxing issignal TEMP : std_logic_vector(3 downto 0);beginprocess(clk) begin if clk'event and clk='1' then if load = '1' then TEMP <= d; el

3、sif TEMP="1000" then TEMP<= TEMP(0) & TEMP(3 downto 1); elsif TEMP="0100" then TEMP<= TEMP(0) & TEMP(3 downto 1); elsif TEMP="0010" then TEMP<= TEMP(0) & TEMP(3 downto 1); elsif TEMP="0001" then TEMP<= TEMP(0) & TEMP(3 downto 1); el

4、se TEMP<="1000" end if; end if; end process; q <= TEMP;end architecture;（2）节日彩灯 源程序：library IEEE;use IEEE.std_logic_1164.all;entity caideng is port ( clk : in std_logic; shift : in std_logic; q : out std_logic_vector(3 downto 0);end entity;architecture shft_reg_arch of caideng issign

5、al temp : std_logic_vector(3 downto 0);begin q<=temp; process(clk) begin if (clk'event and clk='1') then if shift='1' then case temp is when "0000"=>temp<="1000" when "1000"=>temp<="1100" when "1100"=>temp<=&q

6、uot;1110" when "1110"=>temp<="1111" when "1111"=>temp<="0111" when "0111"=>temp<="0011" when "0011"=>temp<="0001" when "0001"=>temp<="0000" when others=>temp<=

7、"0000" end case; else case temp is when "0000"=>temp<="0001" when "0001"=>temp<="0011" when "0011"=>temp<="0111" when "0111"=>temp<="1111" when "1111"=>temp<="1110" when "1110"=>temp<="1100" when "1100"=>temp<="1000" when "1000"=>temp<="0000" when others=>temp<="0000" end case; end if; end if; end process ;end architecture;状态转换图：当shift=1时当shift=0时四：实验测量记录（数据、