EDA第3章补充2-毛刺

1、11. Setup/Hold Time Problem2建立时间和保持时间建立时间和保持时间 建立时间（setup time）是指在触发器的时钟信号上升沿到来以前，数据稳定不变的时间，如果建立时间不够，数据将不能在这个时钟上升沿被打入触发器。保持时间（hold time）是指在触发器的时钟信号上升沿到来以后，数据稳定不变的时间， 如果保持时间不够，数据同样不能被打入触发器(如上图)。 数据稳定传输必须满足建立和保持时间的要求，EDA开发软件可以自动计算两个相关输入的建立和保持时间3Example 14My Waveform InputSetup time = 2nsHold time = 0.

2、1nsAccording to Setup/Hold Matrix Setup time needs = 2.2nsHold time needs = 0.7nsHow to fix ?It is easy. Extend the Setup time from 2ns to 2.2ns Extend the Hold time from 0.1ns to 0.7ns5Correct WaveformExtend the Setup/Hold time to remove the errorWe fix the simulation error. But do we really fix th

3、e error yet ?Simulation : means all the INPUT WAVEFORM is designer provided. We can easily adjust the INPUT WAVEFORM to remove the simulation error. We need to confirm that the REAL INPUT WAVEFORM full fill the Setup/Hold time requirement. 6Example 2All the Setup/Hold prblem between this two FF7How

4、to fix the problemLet us run the Register Performance Timing AnalysisThe Input Clock Frequency is only 3.2ns width 300MHz8ConclusionIf the Setup/Hold time error happen on the Input Register (Example 1)run the Setup/Hold time Matrix to get informationadjust the Input Waveform but double confirm with

5、the real time operation signalIf the Setup/Hold time error happen between Two Register (Example 2)run the Register Performance to get Fmaxmake sure that the input clock frequency is less than or equal to the Fmax92. Design of Combinational Circuit10What is Combinational CircuitCombinational Circuit

6、ifOutputs at a specificed time are a function only of the at that timeexample of combinational circuitaddress decodersmultiplexersadders11The Simplest Combinational CircuitNothing can be simplest than 2 input AND Gate or 2 input OR Gate2 input AND/OR gate is as simple as 1+1 = 2Altera Device can not

7、 handle this so Simple Circuit122 input AND Gate Input WaveformOutput WaveformWhat happen ?But are you sure it is really so Simple ?13Take a closer lookLook at the Delay MatrixWhat is it means ?Assume the AND gate internaldelay is 0.2nsSimple Arithmetic CalculationFor Signal b :(Trace delay of b) +

8、AND gate internal delay = 8.1ns(Trace delay of b) + 0.2ns = 8.1ns(Trace delay of b) = 7.9nsFor Signal a :(Trace delay of a) + AND gate internal delay = 11.1ns(Trace delay of a) + 0.2ns = 11.1ns(Trace delay of a) = 10.9ns14续续Time : 0ns1-00-1001(Trace delay of b) = 7.9ns(Trace delay of a) = 10.9nsTime

9、 : 7.9ns01011Time : 8.1ns01111Time : 10.9ns01110Time : 11.1ns01010Output C change from “0” to “1” at 8.1nsA 3 ns Pulse generate (10.9-7.9 = 3ns)Output C change back from “1” to “0” as the final result15Key Point of Combinational DesignDesign with 2 input AND gate is not as easy as 1+1=2We need to co

10、nsider the Trace Delay and Gate Delay for Combinational Logic: The output of C is “0” : The output of C has a Glitch with 3ns widthIn this example, the 3ns Glitch is caused by Trace DelayEngineer Design Circuit work with not only16续续If you want your cirucit work RELIABLE, you need to consider This i

11、s not Altera Device ProblemThis is Design Problem17Go back to the First ExampleNow, we all know that a 2 input AND gate when involve with timing is not as easy as 1+1=218ReminderWhen Glitch will happenwhen more than one signals change at the same timeWhen you design combinational logicGlitch happen

12、is expectedIf you do not get one, you are lucky onlyA good engineer always remember that Combinational logic will have GLITCH 19Glitch issueIf we know how Glitch generatewe can calculate the exact time when the Glitch comes outwe can calculate the exact pulse width of the GlitchSpecial care must be

13、pay attention when the Combinational Logic output is used for of the Flip-Flop of the Flip-Flop of the Flip-Flopof the Latch20ConclusionCombinational Logic is easy to designWithout special care, Combinational Logic will give you unexpect Glitch and kill your design21PLD内部毛刺产生的原因我们在使用分立元件设计数字系统时，由于PC

14、B走线时，存在分布电感和电容，所以几纳秒的毛刺将被自然滤除。而在PLD内部决无分布电感和电容，所以在PLD/FPGA设计中，竞争和冒险问题将变的较为突出。22FPGA中的冒险现象信号在FPGA器件内部通过连线和逻辑单元时，都有一定的延时。延时的大小与连线的长短和逻辑单元的数目有关，同时还受器件的制造工艺、工作电压、温度等条件的影响。信号的高低电平转换也需要一定的过渡时间。由于存在这两方面因素，多路信号的电平值发生变化时，在信号变化的瞬间，组合逻辑的输出有先后顺序，并不是同时变化,往往会出现一些不正确的尖峰信号，这些尖峰信号称为毛刺。如果一个组合逻辑电路中有毛刺出现，就说明该电路存在冒险。（与分立元件不同，由于PLD内部不存在寄生电容电感，这些毛刺将被完整的保留并向下一级传递，因此毛刺现象在PLD、FPGA设计中尤为突出）23消除毛刺的方法一消除毛刺的方法一一种方法是在输出信号的保持时间内，用一定宽度的高电平脉冲与输出信号做逻辑“与”运算，由此获取输出信号的电平值。下图说明了这种方法，采样脉冲信号从输入引脚“SAMPLE”引入。从仿真波形上可以看出，毛刺信号出现在“TEST”引脚上，而“OUT”引脚上的毛刺已