六人抢答器设计报告

1、精选优质文档-倾情为你奉上湖南人文科技学院课程设计报告课程名称：VHDL语言与EDA课程设计设计题目： 六人抢答器 系 别： 通信与控制工程系 专 业： 电子信息工程 班 级： 电子信息一班 学生姓名: 学 号: 起止日期: 2009年12月21日 2009年12月30日 指导教师: 教研室主任： 专心-专注-专业指导教师评语： 指导教师签名： 年 月 日成绩评定项 目权重成绩1、设计过程中出勤、学习态度等方面0.22、课程设计质量与答辩0.53、设计报告书写及图纸规范程度0.3总 成 绩 教研室审核意见：教研室主任签字： 年 月 日教学系审核意见： 主任签字： 年 月 日摘 要本次设计在ED

2、A开发平台QUARTUS6.0上利用VHDL语言设计六人抢答器电路。电路中设有六个抢答键，可供六人同时抢答；我们利用一个二十进制计数器,将其输入频率设定为一赫兹,成功实现了二十秒倒计时的功能；我们利用VHDL语言中的IF和CASE语句结合空操作语句NULL实现开始抢答与超前抢答的区别；各个模块配以一时钟频率由蜂鸣器输出可实现抢答成功、超前抢答犯规、超时抢答等各种情况的报警效果；本设计采用的是杭州康芯电子有限公司生产的GW48系列/SOPC/EDA实验开发系统，FPGA目标芯片型号为Altera公司的Cyclone系列中的EPIC6Q240C8。芯片配置成功后锁定引脚下载即可进行硬件测试：选择实

3、验电路结构图NO.5，使CLK1与CLKOCK5相接(接受1024Hz时钟频率)，CLK 与CLOCK0相接(接受1Hz时钟频率)，报警输出接SPEAK，六位选手分别对应实验箱上的16键，键7为抢答开始键，当其未按下就进行抢答则为超前犯规，按下后二十秒倒计时开始，选手进行抢答，按实验箱上的复位键则可重新开始下一轮的抢答。关键词：六人抢答器；数码显示；信号封锁；犯规报警。目 录六人抢答器设计要求抢答台数为6；具有抢答开始后20秒倒计时，20秒倒计时后六人抢答显示超时，并报警；能显示超前抢答台号并显示犯规报警；系统复位后进入抢答状态，当有一路抢答按键按下，该路抢答信号将其余各路抢答信号封锁，同时铃

4、声响起,直至该路按键松开,显示牌显示该路抢答台号。1 总体设计方案论论证与对比1.1 方案一 该方案方框图如图1：二十秒倒计时模块数码管蜂鸣器锁存器模块抢答鉴别模块按键输入图1 方案一方框图在该方案中，由二十秒倒计时模块、抢答鉴别模块、锁存器模块等模块组成3。蜂鸣器和数码管分别起报警和显示台号的作用。但该方案中的数码管显示是由七段显示器的形式来显示台号的，由于实验箱电路结构与按键数目的限定，使得我们没有采用该方案。1.2 方案二 该方案方框图如图2：图2 方案二方框图抢答成功按键判别模块蜂鸣器抢答报警模块数码管 超前抢答判别模块译码器二十秒倒计时 模块按键输入此方案中整个电路主要由超前抢答判别

5、模块、二十秒倒计时模块、抢答成功按键模块、抢答报警模块四个模块组成4。其台号的显示都是将信号送入译码器译码之后再由数码管显示出来，结合前面六位选手的按键及开始键可得实验箱上模式5的电路结构满足硬件测试的要求。所以我们选定该方案来进行我们这次的课程设计。2顶层电路VHDL程序设计顶层电路VHDL程序如下USE ieee.std_logic_1164.all; LIBRARY work;ENTITY jinaghu IS port(rst : IN STD_LOGIC;-抢答开始键clk : IN STD_LOGIC;-计数器时钟输入clk1 : IN STD_LOGIC;-蜂鸣器时钟输入AIN

6、: IN STD_LOGIC_VECTOR(6 downto 1);-选手按键speak : OUT STD_LOGIC;-蜂鸣器cout : OUT STD_LOGIC; -超时抢答报警 shuma : OUT STD_LOGIC_VECTOR(3 downto 0);-抢答成功显示台号数码管shuma1 : OUT STD_LOGIC_VECTOR(3 downto 0);shuma2 : OUT STD_LOGIC _VECTOR(3 downto 0); shuma3 : OUT STD_LOGIC_VECTOR(3 downto 0);shuma4 : OUT STD_LOGIC_V

7、ECTOR(3 downto 0);shuma5 : OUT STD_LOGIC_VECTOR(3 downto 0);shuma6 : OUT STD_LOGIC_VECTOR(3 downto 0);END jinaghu;ARCHITECTURE bdf_type OF jinaghu IS component anjian -元件U1例化PORT(rst : IN STD_LOGIC; AIN6 : IN STD_LOGIC_VECTOR(6 downto 1); shuma : OUT STD_LOGIC_VECTOR(3 downto 0);end component;compon

8、ent chaoqian -元件U2例化PORT(clk1 : IN STD_LOGIC; rst : IN STD_LOGIC; AIN6 : IN STD_LOGIC_VECTOR(6 downto 1); speak : OUT STD_LOGIC; shuma1 : OUT STD_LOGIC_VECTOR(3 downto 0); shuma2 : OUT STD_LOGIC_VECTOR(3 downto 0); shuma3 : OUT STD_LOGIC_VECTOR(3 downto 0); shuma4 : OUT STD_LOGIC_VECTOR(3 downto 0);

9、 shuma5 : OUT STD_LOGIC_VECTOR(3 downto 0); shuma6 : OUT STD_LOGIC_VECTOR(3 downto 0);end component;component daojishi -元件U3例化PORT(clk : IN STD_LOGIC; clk1 : IN STD_LOGIC; rst : IN STD_LOGIC; shuma : IN STD_LOGIC_VECTOR(3 downto 0); speak : OUT STD_LOGIC; cout : OUT STD_LOGIC);end component;componen

10、t qiangdabao -元件U3例化PORT(rst : IN STD_LOGIC; clk1 : IN STD_LOGIC; AIN6 : IN STD_LOGIC_VECTOR(6 downto 1); speak : OUT STD_LOGIC);end component;signalSYNTHESIZED_WIRE_17 : STD_LOGIC_VECTOR(3 downto 0);signalSYNTHESIZED_WIRE_1 : STD_LOGIC;signalSYNTHESIZED_WIRE_2 : STD_LOGIC;signalSYNTHESIZED_WIRE_3 :

11、 STD_LOGIC;signalSYNTHESIZED_WIRE_4 : STD_LOGIC;signalSYNTHESIZED_WIRE_18 : STD_LOGIC_VECTOR(3 downto 0);signalSYNTHESIZED_WIRE_19 : STD_LOGIC_VECTOR(3 downto 0);signalSYNTHESIZED_WIRE_20 : STD_LOGIC_VECTOR(3 downto 0);BEGIN shuma3 = SYNTHESIZED_WIRE_17(3);shuma2 = SYNTHESIZED_WIRE_17(2);shuma1 = SY

12、NTHESIZED_WIRE_17(1);shuma0 = SYNTHESIZED_WIRE_17(0);shuma13 = SYNTHESIZED_WIRE_18(3);shuma12 = SYNTHESIZED_WIRE_18(2);shuma11 = SYNTHESIZED_WIRE_18(1);shuma10 = SYNTHESIZED_WIRE_18(0);shuma23 = SYNTHESIZED_WIRE_19(3);shuma22 = SYNTHESIZED_WIRE_19(2);shuma21 = SYNTHESIZED_WIRE_19(1);shuma20 = SYNTHE

13、SIZED_WIRE_19(0);shuma33 = SYNTHESIZED_WIRE_20(3);shuma32 = SYNTHESIZED_WIRE_20(2);shuma31 = SYNTHESIZED_WIRE_20(1);shuma30 rst, AIN6 = AIN, shuma = SYNTHESIZED_WIRE_17); -参数传递映射语句b2v_inst1 : chaoqian PORT MAP(clk1 = clk1, rst = rst, AIN6 = AIN, speak = SYNTHESIZED_WIRE_1, shuma1 = SYNTHESIZED_WIRE_

14、18, shuma2 = SYNTHESIZED_WIRE_19, shuma3 = SYNTHESIZED_WIRE_20, shuma4 = shuma4, shuma5 = shuma5, shuma6 = shuma6);b2v_inst2 : daojishi PORT MAP(clk = clk, clk1 = clk1, rst = rst, shuma = SYNTHESIZED_WIRE_17, speak = SYNTHESIZED_WIRE_3, cout = cout);b2v_inst3 : qiangdabao PORT MAP(rst = rst, clk1 =

15、clk1, AIN6 = AIN, speak = SYNTHESIZED_WIRE_2);SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_1 OR SYNTHESIZED_WIRE_2 OR SYNTHESIZED_WIRE_3;speak = NOT(SYNTHESIZED_WIRE_4);END;3 单元模块程序设计根据顶层原理图，共分为anjian模块、chaoqian模块、daojishi模块、qiangdabao模块这四个模块。其中anjian模块的功能是锁定抢答成功的选手的台号并显示，chaoqian模块可将超前抢答了的选手台号显示出来并伴随报警，da

16、ojishi模块进行二十秒倒计时并显示超时报警，qiangdabao模块主要是为抢答成功之后提供报警功能2。3.1 二十秒倒计时模块 3.1.1二十秒倒计时模块原理图图3 二十秒倒计时模块3.1.2二十秒倒计时模块VHDL程序设计1library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity daojishi isport (clk,clk1,rst: in std_logic; shuma: inout std_logic_vector(3 downto 0);-主数码管 speak : out

17、 std_logic; cout: inout std_logic);-进位,可用于超时显示 end daojishi;architecture one of daojishi isbeginprocess(clk,rst)variable cqi : std_logic_vector(7 downto 0);begin if (rst=1) and (clkevent and clk=1) then if cqi0); end if; end if; if (cqi20) and (cqi23) then cout=1; else cout=0; end if; if (cout=1) an

18、d (shuma=0000) and (rst=1)then speak=clk1;-无人抢答,超时报警else speak=0;end if;end process;end one;3.2 抢答成功选手按键模块 3.2.1抢答成功选手按键模块原理图图4 抢答成功选手按键模块 3.2.2 抢答成功选手按键模块VHDL程序设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity anjian isport (rst: in std_logic; AIN6: in std_logic_vect

19、or(6 downto 1);-六位选手抢答输入 shuma:out std_logic_vector(3 downto 0);-主数码管 end anjian ;architecture one of anjian isbeginprocess(AIN6,rst)variable temp: std_logic_vector(3 downto 0); beginif rst=1 then if AIN6= then temp:=0000; elsif AIN6= then temp:=0001 ; -1 elsif AIN6= then temp:=0010 ; -2 elsif AIN6=

20、 then temp:=0011 ; -3 elsif AIN6= then temp:=0100 ; -4 elsif AIN6= then temp:=0101 ; -5 elsif AIN6= then temp:=0110 ; -6 else null; end if;end if;shuma=temp;end process;end one;3.3 超前抢答犯规模块 3.3.1超前抢答犯规模块原理图图5 超前抢答犯规模块3.3.2超前抢答犯规模块VHDL程序设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_un

21、signed.all;entity chaoqian isport (clk1,rst: in std_logic; AIN6:in std_logic_vector(6 downto 1); speak : out std_logic; shuma1,shuma2,shuma3:out std_logic_vector(3 downto 0); shuma4,shuma5,shuma6:out std_logic_vector(3 downto 0); end chaoqian;architecture one of chaoqian issignal abc:std_logic_vecto

22、r(6 downto 0);begin abcshuma1=0001;shuma2=0000;shuma3=0000;shuma4=0000;shuma5=0000;shuma6=0000; speakshuma1=0000;shuma2=0010;shuma3=0000;shuma4=0000;shuma5=0000;shuma6=0000; speakshuma1=0000;shuma2=0000;shuma3=0011;shuma4=0000;shuma5=0000;shuma6=0000; speakshuma1=0000;shuma2=0000;shuma3=0000;shuma4=

23、0100;shuma5=0000;shuma6=0000; speakshuma1=0000;shuma2=0000;shuma3=0000;shuma4=0000;shuma5=0101;shuma6=0000; speakshuma1=0000;shuma2=0000;shuma3=0000;shuma4=0000;shuma5=0000;shuma6=0110; speakshuma1=0001;shuma2=0010;shuma3=0000;shuma4=0000;shuma5=0000;shuma6=0000; speakshuma1=0001;shuma2=0000;shuma3=

24、0011;shuma4=0000;shuma5=0000;shuma6=0000; speakshuma1=0001;shuma2=0000;shuma3=0000;shuma4=0100;shuma5=0000;shuma6=0000; speakshuma1=0001;shuma2=0000;shuma3=0000;shuma4=0000;shuma5=0101;shuma6=0000; speakshuma1=0001;shuma2=0000;shuma3=0000;shuma4=0000;shuma5=0000;shuma6=0110; speakshuma1=0000;shuma2=

25、0010;shuma3=0011;shuma4=0000;shuma5=0000;shuma6=0000; speakshuma1=0000;shuma2=0010;shuma3=0000;shuma4=0100;shuma5=0000;shuma6=0000; speakshuma1=0000;shuma2=0010;shuma3=0000;shuma4=0000;shuma5=0101;shuma6=0000; speakshuma1=0000;shuma2=0010;shuma3=0000;shuma4=0000;shuma5=0000;shuma6=0110; speakshuma1=

26、0000;shuma2=0000;shuma3=0011;shuma4=0100;shuma5=0000;shuma6=0000; speakshuma1=0000;shuma2=0000;shuma3=0011;shuma4=0000;shuma5=0101;shuma6=0000; speakshuma1=0000;shuma2=0000;shuma3=0011;shuma4=0000;shuma5=0000;shuma6=0110; speakshuma1=0000;shuma2=0000;shuma3=0000;shuma4=0100;shuma5=0101;shuma6=0000;

27、speakshuma1=0000;shuma2=0000;shuma3=0000;shuma4=0100;shuma5=0000;shuma6=0110; speakshuma1=0000;shuma2=0000;shuma3=0000;shuma4=0000;shuma5=0101;shuma6=0110; speakshuma1=0001;shuma2=0010;shuma3=0011;shuma4=0000;shuma5=0000;shuma6=0000; speakshuma1=0001;shuma2=0010;shuma3=0000;shuma4=0100;shuma5=0000;s

28、huma6=0000; speakshuma1=0001;shuma2=0010;shuma3=0000;shuma4=0000;shuma5=0101;shuma6=0000; speakshuma1=0001;shuma2=0010;shuma3=0000;shuma4=0000;shuma5=0000;shuma6=0110; speakshuma1=0001;shuma2=0000;shuma3=0011;shuma4=0100;shuma5=0000;shuma6=0000; speakshuma1=0001;shuma2=0000;shuma3=0011;shuma4=0000;s

29、huma5=0101;shuma6=0000; speakshuma1=0001;shuma2=0000;shuma3=0011;shuma4=0000;shuma5=0000;shuma6=0110; speakshuma1=0001;shuma2=0000;shuma3=0000;shuma4=0100;shuma5=0101;shuma6=0000; speakshuma1=0001;shuma2=0000;shuma3=0000;shuma4=0100;shuma5=0000;shuma6=0110; speakshuma1=0001;shuma2=0000;shuma3=0000;s

30、huma4=0100;shuma5=0000;shuma6=0110; speakshuma1=0000;shuma2=0010;shuma3=0011;shuma4=0100;shuma5=0000;shuma6=0000; speakshuma1=0000;shuma2=0010;shuma3=0011;shuma4=0000;shuma5=0101;shuma6=0000; speakshuma1=0000;shuma2=0010;shuma3=0011;shuma4=0000;shuma5=0000;shuma6=0110; speakshuma1=0000;shuma2=0010;s

31、huma3=0000;shuma4=0100;shuma5=0101;shuma6=0000; speakshuma1=0000;shuma2=0010;shuma3=0000;shuma4=0100;shuma5=0000;shuma6=0110; speakshuma1=0000;shuma2=0010;shuma3=0000;shuma4=0000;shuma5=0101;shuma6=0110; speakshuma1=0000;shuma2=0000;shuma3=0011;shuma4=0100;shuma5=0101;shuma6=0000; speakshuma1=0000;s

32、huma2=0000;shuma3=0011;shuma4=0100;shuma5=0000;shuma6=0110; speakshuma1=0000;shuma2=0000;shuma3=0011;shuma4=0000;shuma5=0101;shuma6=0110; speakshuma1=0000;shuma2=0000;shuma3=0000;shuma4=0100;shuma5=0101;shuma6=0110; speakshuma1=0000;shuma2=0000;shuma3=0011;shuma4=0100;shuma5=0101;shuma6=0110; speaks

33、huma1=0000;shuma2=0010;shuma3=0000;shuma4=0100;shuma5=0101;shuma6=0110; speakshuma1=0000;shuma2=0010;shuma3=0011;shuma4=0000;shuma5=0101;shuma6=0110; speakshuma1=0000;shuma2=0010;shuma3=0011;shuma4=0100;shuma5=0100;shuma6=0110; speakshuma1=0000;shuma2=0010;shuma3=0011;shuma4=0100;shuma5=0101;shuma6=

34、0000; speakshuma1=0001;shuma2=0000;shuma3=0000;shuma4=0100;shuma5=0101;shuma6=0110; speakshuma1=0001;shuma2=0000;shuma3=0011;shuma4=0000;shuma5=0101;shuma6=0110; speakshuma1=0001;shuma2=0000;shuma3=0011;shuma4=0100;shuma5=0000;shuma6=0110; speakshuma1=0001;shuma2=0000;shuma3=0011;shuma4=0100;shuma5=

35、0101;shuma6=0000; speakshuma1=0001;shuma2=0010;shuma3=0000;shuma4=0000;shuma5=0101;shuma6=0110; speakshuma1=0001;shuma2=0010;shuma3=0000;shuma4=0100;shuma5=0000;shuma6=0110; speakshuma1=0001;shuma2=0010;shuma3=0000;shuma4=0100;shuma5=0101;shuma6=0000; speakshuma1=0001;shuma2=0010;shuma3=0011;shuma4=

36、0000;shuma5=0000;shuma6=0110; speakshuma1=0001;shuma2=0010;shuma3=0011;shuma4=0000;shuma5=0101;shuma6=0000; speakshuma1=0001;shuma2=0010;shuma3=0011;shuma4=0100;shuma5=0000;shuma6=0000; speakshuma1=0000;shuma2=0010;shuma3=0011;shuma4=0100;shuma5=0101;shuma6=0110; speakshuma1=0001;shuma2=0000;shuma3=

37、0011;shuma4=0100;shuma5=0101;shuma6=0110; speakshuma1=0001;shuma2=0010;shuma3=0000;shuma4=0100;shuma5=0101;shuma6=0110; speakshuma1=0001;shuma2=0010;shuma3=0011;shuma4=0000;shuma5=0101;shuma6=0110; speakshuma1=0001;shuma2=0010;shuma3=0011;shuma4=0100;shuma5=0000;shuma6=0110; speakshuma1=0001;shuma2=

38、0010;shuma3=0011;shuma4=0100;shuma5=0101;shuma6=0000; speakshuma1=0001;shuma2=0010;shuma3=0011;shuma4=0100;shuma5=0101;shuma6=0110; speak shuma1=0000;shuma2=0000;shuma3=0000;shuma4=0000;shuma5=0000;shuma6=0000; speak=0; end case; end process;end one;3.4 抢答成功报警模块3.4.1抢答成功报警模块原理图图6 抢答成功报警模块3.4.2抢答成功报警

39、模块VHDL程序设计5library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity qiangdabao isport (rst,clk1: in std_logic; AIN6: in std_logic_vector(6 downto 1); speak : out std_logic); end qiangdabao;architecture one of qiangdabao isbeginprocess(rst,AIN6(1),AIN6(2),AIN6(3),AIN6(4),AIN6(5

40、),AIN6(6) beginif (rst=1) and (AIN6(1) or AIN6(2) or AIN6(3) or AIN6(4) or AIN6(5) or AIN6(6)=1) then speak=clk1;-有人抢答成功,报警 else speak=0;end if; end process;end one;4 六人抢答器电路系统仿真及功能分析与调试4.1 分立模块的仿真4.1.1二十秒倒计时模块的仿真 （1）波形仿真将所编写的二十秒倒计时模块daojishi的程序设为工程，选用Altera公司的Cyclone系列中的EPIC6Q240C8为目标芯片进行仿真。仿真结果如下图

41、：图7 二十秒倒计时模块仿真结果(2)模块功能分析当抢答开始后（rst为1），若二十秒内无人抢答，则报警灯亮（cout为1），同时蜂鸣器进行报警（speak的输出频率为clk1的频率），综上可得二十秒倒计时并超时报警的功能要求。 4.1.2抢答成功选手按键模块的仿真（1）波形仿真 将编写的抢答成功选手按键模块anjian的程序设为工程，选用Altera公司的Cyclone系列中的EPIC6Q240C8为目标芯片进行仿真。仿真结果如下图：图8 抢答成功选手按键模块仿真结果(2)模块功能分析抢答开始后,各位选手可进行抢答,其中最先抢答的选手的台号将显示于数码管shuma上，从仿真波形图上我们可以看出当1号选手最先抢答后，其它选手再按抢答键无效，显示台只显示1号选手的台号。4.1.3超前抢答犯规模块的仿真（1）波形仿真将编写的超前抢答犯规模块chaoqian的程序设为工程，选用Altera公司的Cyclone系列中的EPIC6Q240C8为目标芯片进行仿真。仿真结果如下图9：图9 超前抢答犯规模块仿真结果（2）模块功能分析当开始键为0(未开始)时，无论哪位选手抢答即为超前抢答犯规，其台号将分别显示于各自的数码管上，同时蜂鸣器进行报警。4.1.4抢答成功报警模块（1）波形仿真将编写的抢答成功报警模块qiangdabao的程序设为