器件选型usb芯片tusb4020bi

1、Product FolderOrder NowTools & SoftwareTechnical DocumentsSupport & CommuTUSB4020BIZHCSDZ1C JULY 2015 REVISED APRIL 2018TUSB4020BI 双端口 USB 2.0 集线器1特性双端口 USB 2.0 集线器USB 2.0 集线器 特性 多事务转换器 (MTT) 集线器：两个事务转换器 每个事务转换器具有四个异步端点缓冲器兼容 Type C支持电池充电3说明TUSB4020BI 是一款双端口 USB 2.0 集线器。该器件可在上行端口上提供高速/全速 USB

2、连接，在两个下行端口上提供高速、全速或者低速 USB 连接。当上行端口被连接至一个支持高速和全速/低速连接的电气环境中时，下行端口上的高速和全速/低速 USB 连接被启 用。当上行端口被连接到一个只支持全速/低速连接的电气环境中时，下行端口上的高速连接被禁用。充电下行端口 (CDP) 模式（上行端口已连接） 充电端口 (DCP) 模式（上行端口未连接）DCP 模式符合中国电信行业标准 YD/T 1591- 2009D+/D 分压器模式TUSB4020BI 支持每端口或者成组电源开关和过流保护。按照 USB 主机的要求，一个端口电源单独集线器开关为每个下行端口上电或者断电。同样地，当一个端支持每

3、端口或成组电源开关以及过流告知输入口电源单独集线器感测到一个过流时，它只关可使用可编程 (OTP) 只读器 (ROM)、串行 EEPROM 或 I2C/SMBus 受控接口进行自定义配置：闭到受影响的下行端口的电源。当需要为任一端口供电时，一个成组集线器开关打开到其所有下行端口的电源。只有当所有端口处于电源可被移除的状态时，到下行端口的电源才可被关闭。同样，VID 和 PID端口定制生产商和字串（OTP ROM 不支持）当一个成组集线器感测到一个过流下行端口的电源。时，将关闭所有序列号（OTP ROM 不支持）可使用引脚选择或 EEPROM/I2C/SMBus 受控接口选择应用特性提供 128

4、 位通用唯一标识符 (UUID)支持通过 USB 2.0 上行端口进行板载和系统内OTP/EEPROM 编程单时钟输入，24MHz 晶振或者振荡器无特殊驱动程序要求；可与任一支持 USB 堆叠的操作系统无缝工作48 引脚耐热增强型薄型四方扁平 (HTQFP) 封装(PHP)器件信息(1)(1)如需了解所有可用封装，请参阅数据表末尾的可订购录。附框图USB22应用计算机系统扩展坞监视器机顶盒al ComputerTUSB4020BIType A PortTUSB4020BIUSB 1.1KeyboardAn IMPORTANT NOTICE at the end of this data she

5、et addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.English Data Sheet: SLLSEI0USB 2.0 ConnectionUSB 2.0 HubUSB 2.0 DeviceUSB 2.0 PortUSB 1.1 Device器件型号封装封装（标称值）TUSB4020BIHTQFP (48)7.00mm &#

6、215; 7.00mmTUSB4020BIZHCSDZ1C JULY 2015 REVISED APRIL 2018目录1234567特性1应用1说明1修订历史2说明 （续）3Pin Configuration and Functions3Specifications78.5 Programming138.6 Register Maps14Application and Implementation269.1 Application Information269.2 Typical Applications27Power Supply Recommendations3391010.110.21

7、0.3Power Supply33Downstream Port Power33Ground337.17.27.37.47.57.67.7Absoluteum Ratings7ESD Ratings7Recommended Operating Conditions7Thermal Information73.3-V I/O Electrical Characteristics8Hub Input Supply Current8Power-Up Timing Requirements911Layout3411.1 Layout Guidelines3411.2 Layout Example35器

8、件和文档支持371212.112.212.312.412.5接收文档更新通知37社区. 378Detailed Description10商标378.18.28.38.4Overview10Functional Block Diagram10Feature Description11Device Functional Modes12静电放告37Glossary3713机械、封装和可订购信息374修订历史Changes from Revision B (June 2017) to Revision CPage Changed the Absoluteum Ratings table, added

9、 pin voltages7Changes from Revision A (March 2016) to Revision BPage Added SMBUS Programming current to the Hub Input Supply Current table8 Added Note to the SMBus Slave Operation section14Changes from Original (July 2015) to Revision APage 删除了特性“DM/DP 极换”12© 20152018, Texas Instruments Incorpo

10、ratedTUSB4020BIZHCSDZ1C JULY 2015 REVISED APRIL 20185说明 （续）TUSB4020BI 下行端口可提供电池充电连接下行端口 (CDP) 握手支持，以此为电池充电 应用 提供支持。未连接上行端口时，该器件还支持充电端口 (DCP) 模式。DCP 模式支持 USB 电池充电并且符合中国电信行业标准YD/T 1591-2009，能够为 USB 器件提供支持。此外，未连接上行端口时，自动模式能够为 BC 器件以及支持分压器模式充电解决方案的器件提供透明支持。TUSB4020BI 能够为包括电池充电支持在内的部分 特性 提供终端搭接配置，还能够通过 O

11、TP ROM、I2C EEPROM 或 I2C/SMBus 受控接口为 PID、VID、自定义端口和物理层配置提供定制支持。使用 I2C EEPROM 或I2C/SMBus 受控接口时，还可以提供定制字串支持。该器件采用 48 引脚耐热增强型薄型四方扁平 (HTQFP) 封装，工业版的工作温度范围为 -40°C 到 85°C。6Pin Configuration and FunctionsPHP Package 48-Pin HTQFPTop ViewVDD136FULLPWRMGMTz/ SMBA1SCL/SMBCLK235GANGED/SMBA2/ HS_UPSDA/S

12、MBDAT334VDDPWRCTL1/BATEN1433VDD33OVERCUR1z532RSVDPWRCTL2/BATEN2631RSVDThermalPadVDD33730VDDOVERCUR2z829RSVDUSB_VBUS928RSVDTEST1027USB_DM_UPGRSTz1126USB_DP_UPVDD1225VDD33Not to scale3Copyright © 20152018, Texas Instruments IncorporatedVDD331348VDD33USB_DP_DN21447RSVDUSB_DM_DN21546RSVDRSVD1645VDD

13、RSVD1744RSVDVDD1843RSVDRSVD1942USB_DM_DN1RSVD2041USB_DP_DN1PWRCTL_POL2140VDD33SMBUSz2239XOVDD332338XIUSB_R12437VDD33TUSB4020BIZHCSDZ1C JULY 2015 REVISED APRIL 2018Pin Functions(1) I = input, O = output, I/O = input/output, PU = internal pullup resistor, PD = internal pulldown resistor, and PWR = pow

14、er signal4Copyright © 20152018, Texas Instruments IncorporatedPINTYPE(1)DESCRIPTIONNAMENO.CLOCK AND RESET SIGNALSGRSTz11I PUGlobal power reset. This reset brings all of the TUSB4020BI internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional.XI38

15、ICrystal input. This terminal is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 1-M feedback resistor is required between XI and XO.XO39OCrystal output. This terminal is the crystal output for the int

16、ernal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 1-M feedback resistor is required between XI and XO.USB UPSTREAM SIGNALSUSB_DP_UP26I/OUSB high-speed differential transceiver (positive)USB_DM_UP27I/OUSB high-speed differential trans

17、ceiver (negative)USB_R124IPrecision resistor reference. A 9.53-k ±1% resistor should be connected between USB_R1 and GND.USB_VBUS9IUSB upstream port power monitor. The VBUS detection requires a voltage divider. The signal USB_VBUS must be connected to VBUS through a 90.9-k ±1% resistor, an

18、d to ground through a 10-k ±1% resistor from the signal to ground.USB DOWNSTREAM SIGNALSUSB_DP_DN141I/OUSB high-speed differential transceiver (positive) downstream port 1.USB_DM_DN142I/OUSB high-speed differential transceiver (negative) downstream port 1.PWRCTL1/BATEN14I/O PDUSB port 1 power-o

19、n control for downstream power or battery charging enable. The terminal is used for control of the downstream power switch for Port 1.In addition, the value of the terminal is sampled at the deassertion of reset to determine he value of the battery charging support for Port 1 as indicated in the Bat

20、tery Charging Support register.0 = Battery charging not supported 1 = Battery charging supportedOVERCUR1z5I PUUSB DS port 1 overcurrent detection input. This terminal is used to connect the over current output of the downstream port power switch for port 1.0 = An overcurrent event has occurred1 = An

21、 overcurrent event has not occurredIf power management is enabled, the external circuitry needed should be determined by the power switch. In ganged mode, either OVERCUR1z or OVERCUR2z can be used. In ganged mode, the overcurrent will be reported as a hub event instead of a port event.USB_DP_DN214I/

22、OUSB high-speed differential transceiver (positive) downstream port 2.USB_DM_DN215I/OUSB high-speed differential transceiver (negative) downstream port 2.PWRCTL2/BATEN26I/O PDPower-on control /battery charging enable for downstream port 2. This terminal is used for control of the downstream power sw

23、itch for port 2.The value of the terminal is sampled at he deassertion of reset to determine the value of the battery charging support for port 2 as indicated in the Battery Charging Support register.0 = Battery charging not supported 1 = Battery charging supportedOVERCUR2z8I PUOvercurrent detection

24、 for downstream port 2. This terminal is used to connect he over current output of the downstream port power switch for port 2.0 = An overcurrent event has occurred1 = An overcurrent event has not occurredIf power management is enabled, the external circuitry needed should be determined by the power

25、 switch. In ganged mode either OVERCUR1z or OVERCUR2z can be used. In ganged mode the overcurrent will be reported as a hub event instead of a port event.TUSB4020BIZHCSDZ1C JULY 2015 REVISED APRIL 2018Pin Functions (continued)5Copyright © 20152018, Texas Instruments IncorporatedPINTYPE(1)DESCRI

26、PTIONNAMENO.I2C/SMBUS SIGNALSSCL/SMBCLK2I/O PDI2C clock/SMBus clock. Function of terminal depends on the setting of the SMBUSz input.When SMBUSz = 1, this terminal acts as the serial clock interface for an I2C EEPROM. When SMBUSz = 0, this terminal acts as the serial clock interface for an SMBus hos

27、t.This pin must be pulled up to use the OTP ROM.Can be left unconnected if external interface not implemented.SDA/SMBDAT3I/O PDI2C data/SMBus data. Function of terminal depends on he setting of the SMBUSz input.When SMBUSz = 1, this terminal acts as the serial data interface for an I2C EEPROM. When

28、SMBUSz = 0, this terminal acts as the serial data interface for an SMBus host.This pin must be pulled up to use the OTP ROM.Can be left unconnected if external interface not implemented.TEST AND MISCELLANEOUS SIGNALSSMBUSz22I PUSMBUS mode.The value of the terminal is sampled at he deassertion of res

29、et to enable I2C or SMBus mode.0 = SMBus mode selected 1 = I2C mode selectedAfter reset, this signal is driven low by the TUSB4020BI. Due to this behavior, it is recommended to not tie directly to supply but instead pull-up or pull-down using external resistor.PWRCTL_POL21I/O PDPower control polarit

30、y.The value of the terminal is sampled at he deassertion of reset to set the polarity of PWRCTL2:1.0 = PWRCTL polarity is active high. 1 = PWRCTL polarity is active low.After reset, this signal is driven low by the TUSB4020BI. Due to this behavior, it is recommended to not tie directly to supply but

31、 instead pull-up or pull-down using external resistor.GANGED/SMBA2/ HS_UP35I PUGanged operation enable/SMBus address bit 2/ high-speed status for upstream portThe value of the terminal is sampled at he deassertion of reset to set the power switch and over current detection mode as follows:0 = Indivi

32、dual power control supported when power switching is enabled. 1 = Power control gangs supported when power switching is enabled.When SMBus mode is enabled usinBUSz, this terminal sets the value of the SMBus slave address bit 2. SMBus slave address bits 2 and 3 are always 1 for the TUSB4020BI.After r

33、eset, this signal indicates the high-speed USB connection status of the upstream port. A value of 1 indicates the upstream port is connected to a high-speed USB capable port.Note: Individual power control must be enabled for battery charging applications.FULLPWRMGMTz/ SMBA136I, PUFull power manageme

34、nt enable/ SMBus Address bit 1.The value of the terminal is sampled at he deassertion of reset to set the power switch control follows: 0 = Power switching supported1 = Power switching not supportedFull power management is the ability to control power to the downstream ports of the TUSB4020BI using

35、PWRCTL2:1/BATEN2:1.When SMBus mode is enabled usinBUSz, this terminal sets the value of the SMBus slave address bit 1. SMBus slave address bit 3 is always 1 for the TUSB4020BI.Can be left unconnected if full power management and SMBus are not implemented.After reset, this signal is driven low by the

36、 TUSB4020BI. Due to this behavior, it is recommended to not tie directly to supply but instead pull-up or pull-down using external resistor.Note: Power switching must be supported for battery charging applications.RSVD16, 17, 19,20, 28, 29,31, 32, 43,44, 46, 47I/O. These pins are for internal use on

37、ly and should be left unconnected on PCB.TEST10I PDTEST mode enable. When this terminal is asserted high at reset enables test mode. This terminal is for factory use. It is recommended to pull-down this terminal to ground.POWER AND GROUND SIGNALSVDD1, 12, 18, 30,34, 45PWR1.1-V power railTUSB4020BIZH

38、CSDZ1C JULY 2015 REVISED APRIL 2018Pin Functions (continued)6Copyright © 20152018, Texas Instruments IncorporatedPINTYPE(1)DESCRIPTIONNAMENO.VDD337, 13, 23, 25,33, 37, 40,48PWR3.3-V power railGNDPADGroundTUSB4020BIZHCSDZ1C JULY 2015 REVISED APRIL 20187Specificationsum Ratings(1)7.1 Absoluteover

39、 operating free-air temperature (unless otherwise noted)(1) Stresses beyond those listed under Absoluteum Ratinay cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Re

40、commendedOperating Conditions. Exposure to absolute-um-rated conditions for extended periods may affect device reliability.7.2 ESD Ratings(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allo

41、ws safe manufacturing with a standard ESD control process.7.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)(1) A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum andum supply conditions are met.7.4 Thermal Information(1) For more info

42、rmation about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.7Copyright © 20152018, Texas Instruments IncorporatedTHERMAL METRIC(1)TUSB4020BIUNITPHP (HTQFP)48 PINSRJAJunction-to-ambient thermal31.8°C/WRJC(top)Junction-t

43、o-case (top) thermal16.1°C/WRJBJunction-to-board thermal13°C/WJTJunction-to-top characterization parameter0.5°C/WJBJunction-to-board characterization parameter12.9°C/WRJC(bot)Junction-to-case (bottom) thermal0.9°C/WMINNOMMAXUNITVDD (1)1.1-V supply voltage0.991.11.26VVDD333.3

44、-V supply voltage33.33.6VUSB_VBUSVoltage at USB_VBUS pin01.155VTAOperating free-air temperature range402585°CTJOperating junction temperature range4025105°CVALUEUNITV(ESD)Electrostatic dischargeHuman body m(HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)±4000VCharged device m(CDM), per

45、JEDEC specification JESD22-C101, all pins(2)±1500MINMAXUNITSupply VoltageVDD Steady-state supply voltage0.31.4VVDD33 Steady-state supply voltage0.33.8VVoltageUSB_VBUS pin0.31.4VXI pins0.32.45VAll other pins0.33.8VTstgStorage temperature65150°CTUSB4020BIZHCSDZ1C JULY 2015 REVISED APRIL 2018

46、7.5 3.3-V I/O Electrical Characteristicsover operating free-air temperature range (unless otherwise noted)(1) Applies to external inputs and bidirectional buffers(2) Applies to external outputs and bidirectional buffers(3) Applies to GRSTz(4) Applies to pins with internal pullups/pulldowns(5) Applie

47、s to external input buffers7.6 Hub Input Supply Currenttypical values measured at TA = 25°C8Copyright © 20152018, Texas Instruments IncorporatedPARAMETERVDD33VDD11UNIT3.3 V1.1 VLOW-POWER MODESPower-on (after reset)539mADisconnect from host539mASuspend539mAACTIVE MODES (US STATE / DS STATE)

48、2.0 host / 1 HS device active4871mA2.0 host / 2 HS devices active6080mASMBUS Programming current79225mAPARAMETEROPERATIONTEST CONDITIONSMINTYPMAXUNITVIHHigh-level input voltage(1)VDD332VDD33VVILLow-level input voltage(1)VDD3300.8VVIInput voltage0VDD33VVOOutput voltage(2)0VDD33VttInput transition tim

49、e (trise and tfall)025nsVhysInput hysteresis (3)0.13 × VDD33VVOHHigh-level output voltageVDD33IOH = 4 mA2.4VVOLLow-level output voltageVDD33IOL = 4 mA0.4VIOZHigh-impedance, output current(2)VDD33VI = 0 to VDD33±20µAIOZPHigh-impedance, output current with internal pullup or pulldown re

50、sistor(4)VDD33VI = 0 to VDD33±225µAIIInput current (5)VDD33VI = 0 to VDD33±15µATUSB4020BIZHCSDZ1C JULY 2015 REVISED APRIL 20187.7 Power-Up Timing Requirements(1)An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms

51、 power-up delay counting from both power supplies being stable to the de-assertion of GRSTz.There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 s before the VDD33.MISC pins sampled at deassertion of GRSTz

52、: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN4:1, and AUTOENz.(2)(3)Td2 GRSTzVDD33Td1VDDTsu_ioThd_io MISC_IOFigure 1.Power-Up Timing Requirements9Copyright © 20152018, Texas Instruments IncorporatedMINNOMMAXUNITtd1VDD33 stable before VDD stable (1)see (2)mstd2VDD and VDD33 stable before deassertion of GRSTz3mstsu_ioSetup for MISC inputs (3) sampled at the deassertion of GRSTz0.1µsthd_ioHold for MISC inputs(3) sampled at the deassertion of GRSTz.0.1µstVDD33_RAMP VDD33 supply ramp requirements0.2100mstVDD_RAMPVDD supply ramp requirements0.2100msTUSB4020BIZHCSDZ1C JUL