38译码器的VHDL设计

1、3-8译码器的VHDL设计1.实体框图2.程序设计正确的程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECODER38A IS PORT(A2,A1,A0,S1,S2,S3:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY DECODER38A;ARCHITECTURE ONE OF DECODER38A ISSIGNAL S: STD_LOGIC_VECTOR(5 DOWNTO 0); BEGINS<=A2&A1&A0&S1&S2

2、&S3; WITH S SELECT Y<="11111110" WHEN "000100", "11111101" WHEN "001100", "11111011" WHEN "010100", "11110111" WHEN "011100", "11101111" WHEN "100100", "11011111" WHEN "101100&qu

3、ot;, "10111111" WHEN "110100", "01111111" WHEN "111100", "11111111" WHEN OTHERS;END ARCHITECTURE ONE;3.仿真波形图4.仿真波形分析当S1 S2 S3=100时，只有当A2 A1 A0=111时，Y7才输出低电平，否则为高电平，当A2 A1 A0=110时，Y6才输出低电平，否则为高电平，当A2 A1 A0=101时，Y5才输出低电平，否则为高电平，Y4到Y0同理。可见该程序设计的是3-8译码器三

4、、共阳极数码管七段显示译码器的VHDL设计1.实体框图2.程序设计正确的程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DISPLAY_DECODER IS PORT(A3,A2,A1,A0:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END ENTITY DISPLAY_DECODER;ARCHITECTURE ONE OF DISPLAY_DECODER ISSIGNAL S: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINS<=A3&A2&

5、;A1&A0; WITH S SELECT Y<="1111110" WHEN "0000", "0110000" WHEN "0001", "1101101" WHEN "0010", "1111001" WHEN "0011", "0110011" WHEN "0100", "1011011" WHEN "0101", "1011

6、111" WHEN "0110", "1110000" WHEN "0111", "1111111" WHEN "1000", "1111011" WHEN "1001", "0000000" WHEN OTHERS;END ARCHITECTURE ONE;3.仿真波形图4.仿真波形分析由图可知，当A3 A2 A1 A0=0000时，输出Y6到Y0对应为1111110，即只有g不亮，数码管显示为0，A3 A2 A1 A0=0001时，输出对应为0110000，数码管显示为1，