组成原理课程设计逻辑运算器多路开关

1、姓名：学号：指导教师：实验地址：日期：实验名称：多路开关，逻辑运算部件，移位器设计一、实验目的及要求二、实验环境三、实验内容与步骤实验步骤1）新建工程，并为其分配器件及设备。2）新建一个BlockDiagram其名称为ldb2,并编写veriloghdl代码，设计多路开关。3）并为ldb2调试生成一个时序波形图，进行仿真验证。4）新建一个工程，并为其分配器件及设备。5）新建一个BlockDiagram其名称为ldb3,并编写veriloghdl代码，设计逻辑运算部件。6）并为13调试生成一个时序波形图，进行仿真验证。7）新建一个工程，并为其分配器件及设备。四、调试过程及实验结果1）新建一个工程

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6、iih|取.消3)ldb2工程的代码编写32y|gCorrplabonRepat-Fb/Surmaiy|也I2.w>f国12module12c,dzsel,q|;parameterwidc.h=B;解3input1:0sei;A?4inputwidch-l:0a也c/d;55outputvidth-1:0q;IT67reguidth-1:0q;8alvays0(aortoorcordorsei)亘9Hcase(sei)ID2'bOO:q=a;/4112'1:q=D；%1221biO:q=c;132'bll:q=d;*endearc415enctojdule血161

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