单片机中英文

1、An Overview of AT89S51The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction s

2、et and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a hig

3、hly-flexible and cost-effective solution to many embedded control applications. Features：Compatible with MCS.-51 Products4K Bytes of In-System Programmable (ISP) Flash MemoryEndurance: 1000 Write/Erase Cycles4.0V to 5.5V Operating RangeFully Static Operation: 0 Hz to 33 MHzThree-level Program Memory

4、 Lock128 x 8-bit Internal RAM32 Programmable I/O LinesTwo 16-bit Timer/CountersSix Interrupt SourcesFull Duplex UART Serial ChannelLow-power Idle and Power-down ModesInterrupt Recovery from Power-down ModeWatchdog TimerDual Data PointerPower-off FlagFast Programming TimeFlexible ISP Programming (Byt

5、e and Page Mode)Green (Pb/Halide-free) Packaging OptionThe AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-

6、chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue

7、 functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.VCC：Supply voltage (all packages except 42-PDIP).GND：Ground (all packages except 42-PDIP; for 42-PDIP GND connects only the logi

8、c core and the embedded program memory).VDD：Supply voltage for the 42-PDIP which connects only the logic core and the embedded program memory.PWRVDD：Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application board MUST connect both VDD and PWRVDD to the board supply volt

9、age.PWRGND：Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly connected through the common silicon substrate, but not through any metal link. The application board MUST connect both GND and PWRGND to the board ground.Port 0：Port 0 is an 8-bit open drain bi-dire

10、ctional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode,

11、 PO has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffe

12、rs can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (lip) because of the internal pull-ups.Port 2：Port 2 is an 8-bit bi-directi

13、onal I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (lip) because

14、of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVXDPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data

15、 memory that use 8-bit addresses (MOVXRI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The P

16、ort 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (lip) because of the pull-ups.Port 3 receives some contro

17、l signals for Flash programming and verification.Port 3 also serves the functions of various special features of the AT89S51，as shown in the following table.P3 port can also be used as a number of special features AT89C51 mouth, the following table:PinAlternative functionP3.0 RXD（Serial input）P3.1 T

18、XD（Serial output）P3.2 （External interrupt 0）P3.3 （External interrupt 1）P3.4 T0（Timer 0 External input）P3.5 T1（Timer 1 External input）P3.6 （External data memory write strobe）P3.7 （External data memory read strobe）RST：Reset input. A high on this pin for two machine cycles while the oscillator is runni

19、ng resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROG：Address Latch Enable (ALE) is an output

20、pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes

21、. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-

22、disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable (PSEN) is the read strobe to external program memory.When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations

23、are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at OOOOH up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally la

24、tched on reset. EA should be strapped to Vcc for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverti

25、ng oscillator amplifierSpecial Function Registers：Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software shou

26、ld not write 1 s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Interrupt Registers:The individual interrupt enable bits are in the IE register. Two priorities can be set for e

27、ach of the five interrupt sources in the IP register.Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DPO at SFR address locations 82H-83H and DP1 at 84H-85H.Bit DPS=0 in SFR AUXR1 selects DPO and DP

28、S=1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to "1”during power up. It can be set and rest under sof

29、tware control and is not affected by reset.Memory Organization：MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.Program Memory：If the EA pin is connected to GND, all program fetches are directed t

30、o external memory. On the AT89S51，if EA is connected to Vcc, program fetches to addresses OOOOH through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.Data Memory：The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are acc

31、essible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.Watchdog Timer (One-time Enabled with Reset-out)：The WDT is intended as a recovery method in situations where the CPU may be subjected to

32、software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01 EH and OE1 H in sequence to the WDTRST register(SFR location OA6H). When the WDT is enabled, it will increment

33、every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin

34、.The use of watchdog (WDT):WDT to be open to write 01EH and 0E1H in sequence to WDTRST registers (SFR's address 0A6H), when the WDT opened, take some time to 01EH and 0E1H to WDTRST count register in order to avoid WDT overflow. WDT counter 14 count reached 16383 (3FFFH), WDT will overflow and r

35、eset the device. WDT is turned on, it will be with the crystal oscillator in each machine cycle count, which means that users must be less than 16,383 machines each cycle reset WDT, that is to write 01EH and 0E1H to WDTRST register, WDTRST write only register. WDT counter can not be read neither wri

36、te, when the WDT overflows, it is usually RST pin will reset the output of high pulse. Reset pulse duration for the 98 × Tosc, and Tosc = 1/Fosc (crystal oscillation frequency).In order to optimize the work WDT must be at the right time code WDT reset periodically to prevent the WDT overflow.89

37、 s51 SCM interrupt system is introduced.1. interrupt: the execution of a program, allowing external or internal events through hardware interrupt execution, make its steering for handling internal events in the interrupt service routine to;After finishing the interrupt service program, the CPU to co

38、ntinue the original interrupted process, this process is called the interrupt.2. interrupt source: external and internal events can generate interrupts.89 s51 has five interrupt source:(1) INT0: external interrupt 0 request, low level effectively.Through P3.2 input pin.(2) the INT1: external interru

39、pt request 1, low level effectively.Through P3.3 input pin.(3) T0 timer/counter 0 overflow interrupt request.(4) TI: timer/counter 1 overflow interrupt request.(5) the TXD/RXD: serial port interrupt request.When the serial port in the completion of a frame of data sent or received, then request the

40、interrupt.Every interrupt source corresponds to an interrupt request flags, they set up in the special function registers TCON and SCON.When the interrupt request interrupt source, the corresponding marks have TCON and SCON respectively the corresponding latches.3. 89 s51 interrupt system has the fo

41、llowing four special function register:(1) the timer control register TCON (6);(2) serial port control register SCON (2);(3) IE interruption allows register;(4) interrupt priority register IP.Among them, the TCON and SCON part is only used to interrupt control.By you of any of the above special func

42、tion register for operation, such as setting or reset all sorts of interrupt control functions can be realized.翻译单片机AT89S51的概述AT89S51是美国ATMEL公司生产的低功耗，高性能CMOS 8位单片机，片内含4k bytes的可系统编程的Flash只读程序存储器，器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准8051指令系统及引脚。它集Flash程序存储器既可在线编程（ISP)也可用传统方法进行编程及通用8位微处理器于单片芯片中，ATMEL公司的功能强大

43、，低价位AT89S51单片机可为您提供许多高性价比的应用场介，可灵活应用于各种控制领域。主要性能参数：·与MCS-51 产品指令系统完全兼容·4k字节在线系统编程(ISP) Flash闪速存储器·1000次擦写周期·4.0-5.5V的工作电压范围·全静态工作模式：0Hz-33MHz·三级程序加密锁·128×8字节内部RAM·32个可编程I/O口线·2个16位定时/计数器·6个中断源·全双工串行UART通道·低功耗空闲和掉电模式·中断可从空闲模式唤醒系统&#

44、183;看门狗(WDT)及双数据指针·掉电标识和快速编程特性·灵活的在线系统编程(ISP一字节或页写模式)功能特性概述：AT89S51提供以下标准功能：4k字节Flash闪速存储器，128字节内部RAM， 32个I/O口线，看门狗（WDT），两个数据指针，两个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89S51可降至0Hz的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时/计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作

45、直到下一个硬件复位。引脚功能说明：·Vcc： 电源电压·GND：地·P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复用口。作为输出口用时，每位能驱动8个TTL逻辑门电路，对端口写1可作为高阻抗输入端用。在访问外部数据存储器或程序存储器时，这组口线分时转换地址(低8位)和数据总线复用，在访问期间激活内部上拉电阻。在Flash编程时，P0 口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。·P1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对端口写1，通

46、过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，囚为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流(In)。Flash编程和程序校验期间 P 1接收低8位地址。·P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对端口写1，通过内部的上拉电阻把端口拉到高电平，此时可作输入口，作输入口使用时，囚为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流(In)。在访问外部程序存储器或16位地址的外部数据存储器(例如执行MOVX DPTR指令)时，P2口送出高 8位地址数据。在访问8位地址的外部

47、数据存储器(如执行MOVX Ri指令)时，P2口线卜的内容(也即特殊功能寄存器（SFR)区中P2寄存器的内容)，在整个访问期间不改变。Flash编程或校验时，P2亦接收高位地址和其它控制信号。·P3口：P3口是一组带有内部上拉电阻的8位双向I/O口。P3口输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对P3 口写入“1”时，它们被内部上拉电阻拉高并可作为输入端口。作输入端时，被外部拉低的P3 口将用上拉电阻输出电流（In）。 P3口除了作为一般的I/O口线外，更重要的用途是它的第二功能。P3 口还接收一些用于Flash闪速存储器编程和程序校验的控制信号。P3口也可作为AT8

48、9C51的一些特殊功能口，如下表所示：管脚备选功能P3.0 RXD（串行输入口）P3.1 TXD（串行输出口）P3.2 （外部中断0）P3.3 （外部中断1）P3.4 T0（记时器0外部输入）P3.5 T1（记时器1外部输入）P3.6 （外部数据存储器写选通）P3.7 （外部数据存储器读选通）·RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片机复位。WDT溢出将使该引脚输出高电平，设置SFR AUXR 的DISRTO位（地址8EH）可打开或关闭该功能。DISRTO位缺省为RESET输出高电平打开状态。·ALE/PROG：当访问外部程序存储器或数

49、据存储器时，ALE(地址锁存允许)输出脉冲用于锁存地址的低8位字节。即使不访问外部存储器，ALE仍以时钟振荡频率的1/6输出固定的正脉冲信号，囚此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。对Flash存储器编程期间，该引脚还用于输入编程脉冲（PROG）。如有必要，可通过对特殊功能寄存器（SFR)区中的8EH单元的D0位置位，可禁正ALE操作。该位置位后，只有一条MOVX和MOVC指令ALE才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE无效。·PSEN：程序储存允许(PSEN)输出是外部程序存储器的读选通信号，当

50、AT89S51由外部程序存储器取指令(数据)时，每个机器周期两次PSEN有效，即输出两个脉冲。当访问外部数据存储器，没有两次有效的PSEN信号。·EA/VPP：外部访问允许。欲使CPU仅访问外部程序存储器(地址为0000H-FFFFH), EA端必须保持低电平(接地)。需注意的是：如果加密位LB1被编程，复位时内部会锁存EA端状态。如EA端为高电平(接Vcc端)，CPU则执行内部程序存储器中的指令。Flash存储器编程时，该引脚加上+12 V的编程电压Vpp。·XTAL 1：振荡器反相放大器及内部时钟发生器的输入端。·XTAL2：振荡器反相放大器的输出端。·特殊功能寄存器：特殊功能寄存器的于片内的空间分布的这些地址并没有全部占用，没有占用的地址亦不可使用，读这些地址将得到一