DDR内存条引脚定义图 管脚定义图

1、DDR内存条引脚定义图 管脚定义图DDR2 SDRAM DIMM 240 pinDDR: Double Data RateDIMM: Dual Inline Memory ModuleSDRAM: Synchronous Dynamic Random Access Memory, Synchronous to Positive Clock Edge.PIN CONFIGURATIONS (Front side / back side)FrontBackPinSymbolPinSymbolPinSymbolPinSymbolPinSymbolPinSymbolPinSymbolPinSymbol

2、1VREF31DQ1961A491VSS121VSS151VSS181VDDQ211DM5/DQS142VSS32VSS62VDDQ92DQS5#122DQ4152DQ28182A3212NC/DQS14#3DQ033DQ2463A293DQS5123DQ5153DQ29183A1213VSS4DQ134DQ2564VDD94VSS124VSS154VSS184VDD214DQ465VSS35VSS65VSS95DQ42125DM0/DQS9155DM3/DQS12185CK0215DQ476DQS0#36DQS3#66VSS96DQ43126NC/DQS9#156NC/DQS12#186CK

3、0#216VSS7DQS037DQS367VDD97VSS127VSS157VSS187VDD217DQ528VSS38VSS68PAR_IN98DQ48128DQ6158DQ30188A0218DQ539DQ239DQ2669VDD99DQ49129DQ7159DQ31189VDD219VSS10DQ340DQ2770A10/AP100VSS130VSS160VSS190BA1220RFU11VSS41VSS71BA0101SA2131DQ12161CB4191VDDQ221RFU12DQ842CB072VDDQ102NC132DQ13162CB5192RAS#222VSS13DQ943CB

4、173WE#103VSS133VSS163VSS193S0#223DM6/DQS1514VSS44VSS74CAS#104DQS6#134DM1/DQS10164DM8/DQS17194VDDQ224NC/DQS15#15DQS1#45DQS8#75VDDQ105DQS6135NC/DQS10#165NC/DQS17#195ODT0225VSS16DQS146DQS876S1#106VSS136VSS166VSS196NC/A13226DQ5417VSS47VSS770DT1107DQ50137RFU167CB6197VDD227DQ5518RESET#48CB278VDDQ108DQ5113

5、8RFU168CB7198VSS228VSS19NC49CB379VSS109VSS139VSS169VSS199DQ36229DQ6020VSS50VSS80DQ32110DQ56140DQ14170VDDQ200DQ37230DQ6121DQ1051VDDQ81DQ33111DQ57141DQ15171CKE1201VSS231VSS22DQ1152CKE082VSS112VSS142VSS172VDD202DM4/DQS13232DM7/DQS1623VSS53VDD83DQS4#113DQS7#143DQ20173NC203NC/DQS13#233NC/DQS16#24DQ1654NC

6、/BA284DQS4114DQS7144DQ21174NC204VSS234VSS25DQ1755ERR_OUT85VSS115VSS145VSS175VDDQ205DQ38235DQ6226VSS56VDDQ86DQ34116DQ58146DM2/DQS11176A12206DQ39236DQ6327DQS2#57A1187DQ35117DQ59147NC/DQS11#177A9207VSS237VSS28DQS258A788VSS118VSS148VSS178VDD208DQ44238VDDSPD29VSS59VDD89DQ40119SDA149DQ22179A8209DQ45239SA0

7、30DQ1860A590DQ41120SCL150DQ23180A6210VSS240SA1Note: Pin 196 is NC for 512MB, or A13 for 1GB and 2GB; pin 54 is NC for 512MB and 1GB, or BA2 for 2GB.Pin DescriptionsPin numbers may not correlate with symbols; refer to Pin Assignment table above for more information.Pin NumbersSymbolTypeDescription195

8、ODT0InputOn-Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, RDQS, RDQS#, CB, and DM. The ODT input will be ignored if disabled via the LOAD MODE command.185, 186CK0, CK0#

9、InputClock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.52CKE0InputClock Enable: CKE (registered HIGH) acti

10、vates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER

11、DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry, POWER-DOWN exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE) are dis

12、abled during SELF REFRESH. CKE is an SSTL_18 input but will detect a LVCMOS LOW level once VDD is applied during first power-up. After Vref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh opera

13、tion VREF must be maintained to this input.193S0#InputChip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the

14、command code.73, 74, 192RAS#, CAS#, WE#InputCommand Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.54 (2GB), 71, 190BA0, BA1, BA2 (2GB)InputBank Address Inputs: BA0BA1/BA2 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0BA1

15、define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.57, 58, 60, 61, 63, 70, 176, 177, 179, 180, 182, 183, 188, 196 (1GB, 2GB)A0A12 (512MB) A0A13 (1GB, 2GB)InputAddress Inputs: Provide the row address for ACTIVE commands, and the column address and

16、auto precharge bit (A10) for Read/ Write commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0BA1/BA2) or all device banks (A10 HIGH). T

17、he address inputs also provide the op-code during a LOAD MODE command. 3, 4, 9, 10, 12, 13, 21, 22, 24, 25, 30, 31, 33, 34, 39, 40, 80, 81, 86, 87, 89, 90, 95, 96, 98, 99, 107, 108, 110, 111, 116, 117, 122, 123, 128, 129, 131, 132, 140, 141, 143, 144, 149, 150, 152, 153, 158, 159, 199, 200, 205, 206

18、, 208, 209, 214, 215, 217, 218, 226, 227, 229, 230, 235, 236DQ0DQ63I/OData Input/Output: Bidirectional data bus.6, 7, 15, 16, 27, 28, 36, 37, 45, 46, 83, 84, 92, 93, 104, 105, 113, 114, 126, 135, 147, 156, 165, 203, 212, 224, 233 125, 134, 146, 155, 164, 202, 211, 223, 232DQS0DQS8, DQS0# DQS17#, DM0

19、DM8 (DQS9 DQS17)I/OData Strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. Input Data Mask: DM is an input mask

20、signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. If RDQS is disabled, DQS0DQS17 become DM0DM8 and DQS

21、9#DQS17# are not used.42, 43, 48, 49, 161, 162, 167, 168CB0CB7I/OCheck Bits.68PAR_INInputParity bit for the address and control bus.55ERR_OUTOutputParity error found on the address and control bus.120SCLInputSerial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transf

22、er to and from the module.101, 239, 240SA0SA2InputPresence-Detect Address Inputs: These pins are used to configure the presence-detect device.119SDAI/OSerial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module.18RESET#InputAsynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power up to ensure that CKE is LOW and DQs are