数字电子时钟

1、目 录 前言:1 一、设计任务:2二、题目分析与整体构思:3 三、硬件电路设计:4四、程序设计:5五、心得体会:6附录:7参考文献:8前言 EDA（Electronic Design Automation）技术作为现代电子设计技术的核心，它依赖功能强大的计算机，在EDA工具软件平台上，对以硬件描述语言HDL（Hardware Description Language）为系统逻辑描述手段完成的设计文件，自动地完成逻辑编译、逻辑化简、逻辑分割、逻辑综合、结构综合（布局布线），以及逻辑优化和仿真测试，直至实现既定的电子系统功能。EDA技术使得设计者的工作仅限于利用软件的方式，即利用硬件描述语言和ED

2、A软件来完成对系统功能的实现。 电子时钟的设计过程就是一个充分利用EDA软件的过程，利用VHDL语言对硬件进行描述，充分利用软件的逻辑综合与仿真的功能完成对电子时钟的设计，然后将程序写入实验箱，实现其电子时钟的各种功能。一、设计任务1、24小时精准计时 2、十、分、秒可调 3、每逢整点让蜂鸣器鸣叫1秒钟（可以自行发挥加上闹钟设置）二、题目分析与整体构思1、24小时精准计数并显示（1）、电子时钟的小时部分是24进制，时与分之间是60进制，分与秒之间也是60进制，那么要完成电子时钟的正常计数，就需要设计两个60进制计数器和一个24进制计数器，并用合适的端口使他们相连接，以满足24小时的精准计数。（

3、2）、显示部分可以做一个数码管模块，另外为了时、分、秒同时显示，需要做一个扫描仪模块。2、时、分、秒可调 可以在各模块中添加按键设置，以满足这一要求。3、每逢整点让蜂鸣器鸣叫一秒种可以做一个整点报时模块，引出一个合适的脉冲，使之满足每逢整点时报时。4、入下图是电子时钟的整体设计思路。三、硬件电路设计（一）、先用VHDL语言对各个模块进行描述，编译通过后，利用综合仿真系统对其进行时序仿真，然后由程序生成各个模块。1、如图根据程序生成各模块（1）、小时模块和其仿真波形（2）、分钟模块及其仿真波形（3）、秒钟模块及其仿真波形（4）、整点报时模块及其仿真波形（5）、数码管模块及其仿真波形（6）、扫描仪

4、模块2、根据各模块连接电路原理图及其仿真波形（二）、管脚的设定四、程序设计（1）、顶层文件library ieee;entity clock_top isport (clk,reset,setmin,sethour,clkdsp:in std_logic;speaker:out std_logic;lamp:out std_logic_vector(2 downto 0);sel:out std_logic_vector(2 downto 0);a,b,c,d,e,f,g,dp:out std_logic);end clock_top;-*architecture a of clock_top

5、 is-*-second counterCOMPONENT secondPORT(clk, reset,setmin: INSTD_LOGIC;daout:out std_logic_vector(6 downto 0);enmin: OUTSTD_LOGIC);END COMPONENT;-*- minute counterCOMPONENT minutePORT(clk, clk1,reset,sethour: INSTD_LOGIC;enhour: OUTSTD_LOGIC;daout:out std_logic_vector(6 downto 0);END COMPONENT;-*-h

6、our counterCOMPONENT hourPORT(clk, reset: INSTD_LOGIC;daout:out std_logic_vector(5 downto 0);END COMPONENT;-*COMPONENT alertPORT(clk: INSTD_LOGIC;dain:in std_logic_vector(6 downto 0);lamp:out std_logic_vector(2 downto 0);speak: OUTSTD_LOGIC);END COMPONENT;-*COMPONENT seltimePORT(clk1, reset: INSTD_L

7、OGIC;sec,min:in std_logic_vector(6 downto 0);hour:in std_logic_vector(5 downto 0);daout:out std_logic_vector(3 downto 0);sel: OUTSTD_LOGIC_vector(2 downto 0);END COMPONENT;-*COMPONENT deledPORT(num: INSTD_LOGIC_vector(3 downto 0);led:out std_logic_vector(6 downto 0);END COMPONENT;-*signal ledout:std

8、_logic_vector(6 downto 0);signal enmin_re,enhour_re: std_logic;signal second_daout,minute_daout:std_logic_vector(6 downto 0);signal hour_daout:std_logic_vector(5 downto 0);signal seltime_daout:std_logic_vector(3 downto 0);-*begina<=ledout(0);b<=ledout(1);c<=ledout(2);d<=ledout(3);e<=l

9、edout(4);f<=ledout(5);g<=ledout(6);dp<='0'u1: second port map(reset=>reset,clk=>clk,setmin=>setmin,enmin=>enmin_re,daout=>second_daout);u2:minute port map(clk=>enmin_re,clk1=>clk,reset=>reset,sethour=>sethour,enhour=>enhour_re,daout=>minute_daout);u3

10、:hour port map(clk=>enhour_re,reset=>reset,daout=>hour_daout);u4:alert port map(clk=>clk,dain=>minute_daout,speak=>speaker,lamp=>lamp);u5:seltime port map(clk1=>clkdsp,reset=>reset,sec=>second_daout,min=>minute_daout,hour=>hour_daout,daout=>seltime_daout,sel=&g

11、t;sel);u6:deled port map(num=>seltime_daout,led=>ledout);end a;（2）、小时模块程序LIBRARY ieee;ENTITY hour ISPORT(clk,reset: INSTD_LOGIC;daout: out std_logic_vector (5 downto 0);END entity hour;ARCHITECTURE fun OF hour ISSIGNAL count: STD_LOGIC_VECTOR( 5 downto 0);BEGIN daout <= count; process ( clk

12、,reset) begin if (reset='0') then count <= "000000" elsif (clk' event and clk='1') then if (count(3 downto 0)="1001") then if (count <16#24#) then count<=count + 7; else count<="000000" end if; elsif(count <16#24#) then count <= cou

13、nt + 1; else count<="000000" end if; end if; end process;END fun;（3）、分钟模块程序LIBRARY ieee;ENTITY minute ISPORT(clk, clk1,reset,sethour : INSTD_LOGIC;enhour : OUTSTD_LOGIC;daout: out std_logic_vector (6 downto 0);END entity minute;ARCHITECTURE fun OF minute ISSIGNAL count: STD_LOGIC_VECTOR

14、( 6 downto 0);BEGIN daout <= count; process ( clk,reset,sethour) begin if (reset='0') then count <= "0000000" elsif (sethour='0') then enhour <= clk1; elsif (clk' event and clk='1') then if (count(3 downto 0)="1001") then if (count <16#60#)

15、 then if (count="1011001") then enhour<='1' count<="0000000" ELSE count<=count+7; end if; else count<="0000000" end if; elsif(count <16#60#) then count <= count + 1; enhour<='0' after 100 ns; else count<="0000000" end if

16、; end if; end process;END fun;（4）、秒种模块程序LIBRARY ieee;ENTITY second ISPORT(clk, reset,setmin : INSTD_LOGIC;enmin : OUTSTD_LOGIC;daout: out std_logic_vector (6 downto 0);END entity second;ARCHITECTURE fun OF second ISSIGNAL count: STD_LOGIC_VECTOR( 6 downto 0);BEGIN daout <= count; process ( clk ,

17、reset , setmin) begin - enmin<=k; if (reset='0') then count <= "0000000" elsif (setmin='0') then enmin <= clk; elsif (clk 'event and clk='1') then if (count(3 downto 0)="1001") then if (count <16#60#) then if (count="1011001") the

18、n enmin<='1' count<="0000000" ELSE count<=count+7; end if; else count<="0000000" end if; elsif (count < 16#60#) then count <= count+1; enmin<='0' after 100 ns; else count<="0000000" end if; end if; end process;END fun;（5）、整点报时模块程序

19、LIBRARY ieee;ENTITY alert ISPORT(clk : INSTD_LOGIC;dain : INSTD_LOGIC_VECTOR(6 DOWNTO 0);speak: OUTSTD_LOGIC);END alert ;ARCHITECTURE fun OF alert ISsignal count : std_logic_vector( 1 downto 0);signal count1: std_logic_vector( 1 downto 0);BEGINspeaker:process (clk)begin speak <= count1(1);if (clk

20、 'event and clk= '1') thenif (dain = "000000") thenif (count1>="10") then count1<="00"elsecount1 <= count1 + 1;end if; end if;end if;end process speaker;END fun ;（6）、数码管模块程序LIBRARY ieee;ENTITY deled ISPORT(num: INstd_logic_vector( 3 downto 0); led:

21、OUT std_logic_vector(6 downto 0);END deled;ARCHITECTURE fun OF deled ISBEGIN led <= "1111110" when num= "0000" else "0110000" when num= "0001" else "1101101" when num= "0010" else "1111001" when num= "0011" else "

22、;0110011" when num= "0100" else "1011011" when num= "0101" else "1011111" when num= "0110" else "1110000" when num= "0111" else "1111111" when num= "1000" else "1111011" when num= "1001"

23、; else "1110111" when num= "1010" else "0011111" when num= "1011" else "1001110" when num= "1100" else "0111101" when num= "1101" else "1001111" when num= "1110" else "1000111" when num= &qu

24、ot;1111" ;END fun;（7）、扫描仪模块程序LIBRARY ieee;ENTITY seltime ISPORT(clk1, reset: INSTD_LOGIC;sec,min : INSTD_LOGIC_VECTOR(6 downto 0);hour : in std_logic_vector (5 downto 0);daout: OUTSTD_LOGIC_vector (3 downto 0);sel : out std_logic_vector ( 2 downto 0);END seltime;ARCHITECTURE fun OF seltime ISSI

25、GNAL count: STD_LOGIC_vector ( 2 downto 0);BEGIN sel <= count; process ( clk1,reset) begin if (reset ='0') then count <= "000" elsif (clk1 'event and clk1='1') then if ( count >= "101") then count <= "000" else count <= count + 1; end if; end if; case count is when "000" => daout <= sec(3 downto 0); when "001" => daout(3) <= '0' daout(2 downto 0) <= sec (6 downto 4); when "010" =