我集成电路基础_6

1、EE141 Digital Integrated Circuits2ndCombinational Circuits1Jan M. RabaeyAnantha ChandrakasanBorivoje NikoliEE141 Digital Integrated Circuits2ndCombinational Circuits2一、静态互补逻辑 二、Ratioed Logic三、差分级联逻辑四、传输管逻辑 五、CPL逻辑六、动态逻辑EE141 Digital Integrated Circuits2ndCombinational Circuits3Combinational Sequenti

2、alOutput = f(In)Output = f(In, Previous In)Combina t i o n alLogicCircuitOutInCombina t i o n alLogicCircuitOutInStateEE141 Digital Integrated Circuits2ndCombinational Circuits4At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a lo

3、w-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on

4、 the capacitance of high impedance circuit nodes. EE141 Digital Integrated Circuits2ndCombinational Circuits5VDDF(In1,In2,InN)In1In2InNIn1In2InNPUNPDNPMOS onlyNMOS onlyPUN and PDN are dual logic networks一、静态互补逻辑一、静态互补逻辑EE141 Digital Integrated Circuits2ndCombinational Circuits6Pulldown Logic Block下拉

5、逻辑块Pullup Logic Block上拉逻辑块 反相器 与非门EE141 Digital Integrated Circuits2ndCombinational Circuits7aout+EE141 Digital Integrated Circuits2ndCombinational Circuits8EE141 Digital Integrated Circuits2ndCombinational Circuits9EE141 Digital Integrated Circuits2ndCombinational Circuits10、上拉网络、上拉网络: PMOS (PMOS衬底

6、：总是接衬底：总是接VDD) 2、下拉网络下拉网络: NMOS (NMOS衬底：总是接衬底：总是接GND)3、 逻辑功能：逻辑功能： 1）NMOS ：串联串联 - 与与 并联并联 - 或或 2） PMOS ：串联串联 - 或或 并联并联 - 与与 3）最后输）最后输 出：取出：取“非非” EE141 Digital Integrated Circuits2ndCombinational Circuits11复杂门复杂门CEDBAZ、上拉网络、上拉网络: PMOS (PMOS衬底：总是接衬底：总是接VDD) 2、下拉网络下拉网络: NMOS (NMOS衬底：总是接衬底：总是接GND)3、 逻辑功

7、能：逻辑功能： 1）NMOS ：串联串联 - 与与 并联并联 - 或或 2） PMOS ：串联串联 - 或或 并联并联 - 与与 3）最后输）最后输 出：取出：取“非非”EE141 Digital Integrated Circuits2ndCombinational Circuits12OUT = D + A (B + C)DABCDABCEE141 Digital Integrated Circuits2ndCombinational Circuits13与或非门与或非门 AOIEE141 Digital Integrated Circuits2ndCombinational Circui

8、ts14EE141 Digital Integrated Circuits2ndCombinational Circuits15EE141 Digital Integrated Circuits2ndCombinational Circuits16EE141 Digital Integrated Circuits2ndCombinational Circuits17用与或非门实现用与或非门实现 “异或异或” “同或同或”功能功能EE141 Digital Integrated Circuits2ndCombinational Circuits18设： kn = 3 * kp nMOS的工艺跨导

9、是pMOS的3倍 VTN = - VTP nMOS与pMOS的阈值电压相同例如：0.5u 工艺 （ p. 47 ） kn = 73uA/V2 kn = 0.7V kp = 73uA/V2 kp = - 0.8V问题：如何设计使噪声容限最好？（延时优化） EE141 Digital Integrated Circuits2ndCombinational Circuits19最好的噪声容限（延时优化）的条件： pMOS network的总跨导 = nMOS network的总跨导由: Id = k (W/L)(Vgs - Vt)(Vds - 0.5 Vds2) 可估计MOS管的跨导: Gn = k

10、n (Wn/Ln) nMOS 跨导 Gp = kp (Wp/Lp) pMOS 跨导pMOSnetworknMOSnetworkVDDVSSoutinputsEE141 Digital Integrated Circuits2ndCombinational Circuits20inout设： kn = 3 * kp nMOS的工艺跨导是pMOS的3倍 VTN = - VTP nMOS与pMOS的阈值电压相同Gn = kn (Wn/Ln) Gp = kp (Wp/Lp) Inverter最佳噪声容限条件 （VTH = VDD/2）： Gn = Gp kn (Wn/Ln) = kp (Wp/Lp)

11、(Wn/Ln) = （ kp / kn ）(Wp/Lp) = （1/3） (Wp/Lp) EE141 Digital Integrated Circuits2ndCombinational Circuits21+baout设： kn = 3 * kp nMOS的工艺跨导是pMOS的3倍 VTN = - VTP nMOS与pMOS的阈值电压相同Gn = kn (Wn/Ln) Gp = kp (Wp/Lp) NAND最佳噪声容限条件 （VTH = VDD/2）： Gn总 = Gp总 kn (Wn/Ln) /2 = 2 kp (Wp/Lp) (Wn/Ln) = （ 4kp / kn ）(Wp/Lp)

12、 = （4/3） (Wp/Lp) EE141 Digital Integrated Circuits2ndCombinational Circuits22+baout设： kn = 3 * kp nMOS的工艺跨导是pMOS的3倍 VTN = - VTP nMOS与pMOS的阈值电压相同Gn = kn (Wn/Ln) Gp = kp (Wp/Lp) NOR最佳噪声容限条件 （VTH = VDD/2）： Gn总 = Gp总 2 kn (Wn/Ln) = kp (Wp/Lp) / 2 (Wn/Ln) = （ 4kp / kn ）(Wp/Lp) = （1/12） (Wp/Lp) EE141 Digi

13、tal Integrated Circuits2ndCombinational Circuits23所有逻辑门有与反相器相同的驱动能力所有逻辑门有与反相器相同的驱动能力BAABFVDDVDDABABFVDDAAF1222221144Inverte r2-input N A N D2-input N O REE141 Digital Integrated Circuits2ndCombinational Circuits24VDDVSSPDNIn1In2In3FRLLoadVDDVSSIn1In2In3FVDDVSSPDNIn1In2In3FVSSPDNResistiveDepletionLoa

14、dPMOSLoad(a) resistive load(b) depletion load NMOS(c) pseudo-NMOSVT 0Goal: to reduce the number of devices over complementary CMOSEE141 Digital Integrated Circuits2ndCombinational Circuits25VDDVSSIn1In2In3FVDDVSSPDNIn1In2In3FVSSPDNDepletionLoadPMOSLoaddepletion load NMOSpseudo-NMOSVT 0EE141 Digital

15、Integrated Circuits2ndCombinational Circuits261）结构结构 Uses a p-type as a resistive pullup, n-type network for pulldowns.nPMOS处于总是弱导通状态n相当于一个大电阻（15K）nNMOS导通电阻约（5K）EE141 Digital Integrated Circuits2ndCombinational Circuits272）Output voltagesnLogic 1 output is always at VDD.nLogic 0 output is above 0.nV

16、OL = 0.25 (VDD) is one plausible choice.EE141 Digital Integrated Circuits2ndCombinational Circuits28 伪伪NMOS逻辑逻辑 (a) 与非门与非门 (b) 或非门或非门3）伪）伪nMOS逻辑门例子逻辑门例子EE141 Digital Integrated Circuits2ndCombinational Circuits29EE141 Digital Integrated Circuits2ndCombinational Circuits30q（1）有静态功耗）有静态功耗.q（2）面积小（）面积小

17、（PMOS比静态门少）比静态门少） n个输入端的与非门、或非门个输入端的与非门、或非门CMOS电路需电路需2n个个MOS管，而相管，而相应的伪应的伪NMOS电路只需电路只需(n+1)个个MOS管。管。q（3）下降时间长）下降时间长. 由于采用由于采用PMOS负载，其电阻约为负载，其电阻约为NMOS的的2 3倍，延迟时间倍，延迟时间 。EE141 Digital Integrated Circuits2ndCombinational Circuits31qDCVSL = differential cascode voltage switch logic （差分级联电压开关逻辑）q属于Static

18、 logic.q延时小 (Uses latch to compute output quickly).q双轨逻辑（Requires true/complement inputs, produces true/complement outputs）.EE141 Digital Integrated Circuits2ndCombinational Circuits32下拉网络采用下拉网络采用NMOS器件，并且两者是互斥的器件，并且两者是互斥的: 左边导通时右边关断左边导通时右边关断; 右边导通时左边关断右边导通时左边关断.EE141 Digital Integrated Circuits2ndC

19、ombinational Circuits33下拉网络采用下拉网络采用NMOS器件，并且两者是互斥的器件，并且两者是互斥的: 左边导通时右边关断左边导通时右边关断; 右边导通时左边关断右边导通时左边关断.EE141 Digital Integrated Circuits2ndCombinational Circuits34BAABBBOutOutXOR-NXOR gate两个下拉网络之间共用了晶体管，从而实现了面积开销的减少。EE141 Digital Integrated Circuits2ndCombinational Circuits35EE141 Digital Integrated

20、Circuits2ndCombinational Circuits36q1）属于静态逻辑.q2）属于双轨逻辑 out和outb有相同的延时q3）延时小. 因为有正反馈加速q4）面积小 因为NMOS多q5）功耗大 因为正反馈时存在短路AAOutOutEE141 Digital Integrated Circuits2ndCombinational Circuits37四、四、Switch logic 开关逻辑开关逻辑nTypes of switches 互补传输管逻辑 (transmission logic) NMOS传输管逻辑 (pass logic)传输门 NMOS传输管利用传输门的逻辑特点

21、，可以简化CMOS逻辑电路。传输门体现了MOS管的双导通特性，为逻辑电路的设计增加了灵活性。以NMOS传输门为例说明传输门的逻辑特点。分析CMOS传输门也只分析其中NMOS管功能即可。EE141 Digital Integrated Circuits2ndCombinational Circuits38VDD00VDDVDDVDD - VtnA = 1时n Y = BAB?Y 但高电平有阈值损失00/VDD高阻2) A = 0时 Y = 高阻XABAY即不定态XEE141 Digital Integrated Circuits2ndCombinational Circuits39(1) 必须用

22、电平恢复电路VDD0VDD - VtVDDVDDVDD - Vtout+EE141 Digital Integrated Circuits2ndCombinational Circuits40(2) 级联时应注意VDDVDD - VtVDDVDD - 2VtVDDVDDVDD - VtVDD不好可以EE141 Digital Integrated Circuits2ndCombinational Circuits41设计时要消除输出的不确定状态EE141 Digital Integrated Circuits2ndCombinational Circuits42需要6个晶体管（产生非, 还要一

23、个反向器4个晶体管（产生B非，要一个反向器EE141 Digital Integrated Circuits2ndCombinational Circuits43问题：传输管逻辑能产生非逻辑吗？非逻辑吗？不能。不能。 传输管逻辑是一种非完备的逻辑。传输管逻辑是一种非完备的逻辑。 （可以实现与、或、非的逻辑是完备的）（可以实现与、或、非的逻辑是完备的）解决方案：使用其他逻辑。解决方案：使用其他逻辑。 （需要非逻辑的部分使用反向器）（需要非逻辑的部分使用反向器）EE141 Digital Integrated Circuits2ndCombinational Circuits44AY=AB +AB

24、EE141 Digital Integrated Circuits2ndCombinational Circuits45ABF00P401P310P211P11234FABPABPABPA BPEE141 Digital Integrated Circuits2ndCombinational Circuits46() NMOS型 ()全传输门型EE141 Digital Integrated Circuits2ndCombinational Circuits47(C) CMOS型 CMOS结构的多路转换开关克服了NMOS结构所存在的传输高电平阈值电压损耗和串联电阻大的问题，但晶体管数目增加了一

25、倍。EE141 Digital Integrated Circuits2ndCombinational Circuits48作业写出电路图的逻辑式EE141 Digital Integrated Circuits2ndCombinational Circuits49五、互补传输（五、互补传输（CPL）逻辑逻辑ABABBBBBABABF=ABF=ABF=A+BF=A+BBBAAAAF=AF=AOR/NOREXOR/NEXORAND/NANDFFPass-TransistorNetworkPass-TransistorNetworkAABBAABBInverse(a)(b)EE141 Digita

26、l Integrated Circuits2ndCombinational Circuits50高性能设计中常使用CPL逻辑。基本思想（类似DCVSL）是接收真输入及其互补输入并产生真输出及其互补输出。特点：、采用差分方式，电路中总是存在互补的数据输入和输出。所以不必增加反向器来得到反信号。EE141 Digital Integrated Circuits2ndCombinational Circuits51、CPL属于静态门类型，因为定义为输出的节点总是通过一个低阻路径连到VDD或GND。、CPL的设计具有模块化的特点。他们都采取完全相同的拓扑结构。只是输入的排列不同。这使得这类单元库的设计

27、非常简单。较复杂的门可以通过串联标准的传输管模块来构成。特点：EE141 Digital Integrated Circuits2ndCombinational Circuits52互补传输逻辑互补传输逻辑与与/与非门与非门或或/或非门或非门ABBABEE141 Digital Integrated Circuits2ndCombinational Circuits53互补传输逻辑互补传输逻辑数据选择器数据选择器同或同或/异或门异或门ABABABEE141 Digital Integrated Circuits2ndCombinational Circuits54四输入与门四输入与门用用CPL

28、实现的四实现的四输入与输入与/与非门，使用与非门，使用的晶体管总数是的晶体管总数是14个个（包括最后的缓冲器）（包括最后的缓冲器）这个数字高于前面讨这个数字高于前面讨论过的门。但是这个论过的门。但是这个结构同时产生了与结构同时产生了与/与与非功能，这可能减少非功能，这可能减少整个电路的晶体管数整个电路的晶体管数目。目。EE141 Digital Integrated Circuits2ndCombinational Circuits55六、六、 Domino LogicUses precharge clock to compute output in two phases: Precharge

29、 (预充电); Evaluate （赋值）.EE141 Digital Integrated Circuits2ndCombinational Circuits56In1In2PDNIn3MeMpClkClkOutCLOutClkClkABCMpMeTwo phase operation Precharge (CLK = 0) Evaluate (CLK = 1)EE141 Digital Integrated Circuits2ndCombinational Circuits57OutClkClkABCMpMeonoff1offon(AB)+C)Two phase operationIn1In2PDNIn3MeMpClkClkOutCL Evaluate (Clk = 1)0011Precharge (Clk = 0)EE141 Digital Integrated Circuits2ndCombinational Circuits58ClkClkOut1InMpMeMpMeClkClkOut2VtClkInOut1Out2VVTnOnly 0 1 transitions allowed at inputs!EE141 Digital Integrated Circuits2ndCombinatio