数字逻辑设计第3章 数字电路

1、Chapter 3 Digital Circuit（数字电路）The electrical aspects of digital circuits（数字电路中的电气知识）1Basic logic functionOR gate0 0 00 1 01 0 01 1 1Truth table （真值表）A B ZZ = A BAND gateNOT gateZ = A + BZ = A0 0 00 1 11 0 11 1 1Truth table （真值表）A B ZA Z0 11 0Truth table （真值表）ABZABZAZ2NAND and NORNAND gate logic exp

2、ression： Z = ( A B ) logic symbol：NOR gate logic expression： Z = ( A + B ) logic symbol：&133.1 Logic Signals and Gates（逻辑信号和门电路）在电路中如何表示0和1？ 高电平（HIGH）和低电平（LOW）高电平对应 0 还是 1？正逻辑positive10负逻辑negative104如何在输入控制下获得高、低电平？VOUTVINVccR获得高、低电平的基本原理当S闭合，Vout=当S断开，Vout=0 VVcc(LOW)(HIGH)对开关的要求？可以做开关的器件S53.2 Logi

3、c Family （逻辑系列）TTL（Transistor Transistor Logic） CMOS（Complementary MOS） ECL（Emitter- Coupled Logic）Chips from the same family have similar input, output, and internal circuit characteristics, but perform different logic function.（同一系列的芯片具有类似的输入、输出及内部电气特性，但逻辑功能不同。）Chips from the same family can be in

4、terconnected to perform any desired logic function.Chips from the different families may not be compatible.（不同系列的芯片可能不匹配）63.3 CMOS Logic CMOS logic levelsLogic 1（HIGH）Logic 0（LOW）5.0V3.5V1.5V0.0VundefinedTypical：5V power supplyOther power supply：3.3V or 2.7V71、MOS TransistorsN-channel and P-channel

5、Normally Vgs = 0 Vgs = 0 Rds is very high（106） 截止状态（off） Vgs Rds 导通状态（on）漏极 drain源极 source栅极 gateVgs+N channel源极 source漏极 drain栅极 gate+VgsP channel8Normally：Vgs 兆欧）无论栅电压如何 栅漏、栅源之间几乎没有电流 （漏电流 leakage current , A）栅极与源和漏极之间有电容耦合 信号转换时，电容充放电，功耗较大1、MOS Transistors10MOS管的基本开关电路vOvIVccR只要电路参数选择合理输入低，截止，输出高

6、输入高，导通，输出低vI+vO+iD+ VDDRDDGS112、Basic CMOS Inverter Circuit工作原理1、VIN = 0.0VVGSN = 0.0V，Tn offVGSP = VIN VDD = 5.0V，Tp onVOUT VDD = 5.0V2、VIN = VDD = 5.0VVGSN = 5.0V，Tn onVGSP = VIN VDD = 0.0V ，Tp offVOUT 0VDD = +5.0VVOUTVINTpTnGDSSVinVoutLOWHIGHHIGHLOW122、 Basic CMOS Inverter CircuitVDD = +5.0VVOUTV

7、INTpTnVinVoutLOWHIGHHIGHLOW一个输入端，实现对两个开关的控制 PMOS开关接1（正电源）NMOS开关接0（接地） 为确保输出具有确定的1或0，开关必须一通一断，不能全通或全断133、CMOS NAND Gate 工作原理：1、either input is LOW T1、T3至少有一个截止， T2、T4至少有一个导通；Z为高（ VDD）2、both inputs are HIGH T1、T3都导通， T2，T4都截止， Z为低（ 0V）VDD = +5.0VZABT1T2T4T3思考：两种开关能否都采用串联形式？144、CMOS NOR Gate工作原理： 1、Bot

8、h inputs are LOW T1、T3都截止， T2，T4都导通， Z为高（ VDD） 2、either input is HIGH T1、T3至少有一个导通， T2、T4至少有一个截止； Z为低（ 0V）VDD = +5.0VZABT1T2T4T315VDD = +5.0VZABVDD = +5.0VZABNOR GateNAND Gate小结：每个输入控制一对互补的晶体管：P接1，N接0； 基本逻辑体现在N网络上，P网络采用对偶形式；由于N网络接地，因此输出反相（非）； 16VDD = +5.0VABZCD5、CMOS AND-OR-INVERT Gates176、CMOS OR-A

9、ND-INVERT Gates187、 Fanin（扇入）The number of inputs that a gate can have in a particular logic family.The additive “on” resistance of series transistors limits the fan-in of CMOS gates.（导通电阻的可加性限制了CMOS门的扇入数）198、Noninverting Gates（非反相门）VDD = +5.0VAZNoninverting buffer（非反相缓冲器）2-input AND gate203.4 Elect

10、rical Behavior of CMOS Circuits（CMOS电路的电气特性）物理上的而不是逻辑上的Logic Voltage levels（逻辑电压电平）DC noise margins（直流噪声容限）Fanout（扇出）Speed（速度）Power consumption（功耗）Noise（噪声）Electrostatic discharge（静电放电）Open-drain outputs（漏极开路输出）Three-state outputs（三态输出）21data sheet（数据表）（P.99）223.5 CMOS Static Electrical Behavior（CMO

11、S稳态电气特性）VDD = +5.0VVOUTVINTpTnVOUTVIN5.01.53.55.0Transfer characteristic 0 1 0123Logic LevelHIGHABNORMALLOWVOLmaxVILmaxVIHminVOHminVOUTVIN5.01.53.55.0Transfer characteristic24HIGHABNORMALLOWVOLmaxVILmaxVIHminVOHminVCC0.1VGND0.1V0.7VCC0.3VCCLogic Level25DC noise margin（直流噪声容限）A measure of how much no

12、ise it takes to corrupt a worst-case output voltage into a value that may not be recognized properly by an input. 门电路的抗干扰能力HIGHABNORMALLOWVOLmaxVILmaxVIHminVOHminHIGH-state DC noise margin：VNH=VOHmin1- VIHmin2LOW-state DC noise margin： VNL=VILmax2- VOLmax1Gate 1Gate 22674HC driving 74HCT HIGH-state:

13、 4.4 2.0 = 2.4V LOW-state: 0.8 0.1 = 0.7V74HCT driving 74HC HIGH-state: 4.4 3.85 = 0.55V LOW-state: 1.35 0.1 = 1.25VCompute the LOW-state and HIGH-state DC noise margins.p.146 Table 3-6 p.147 Table 3-774HC FamilyVOHminC= 4.4VVOLmaxC= 0.1VVIHmin = 3.85VVILmax = 1.35V74HCT FamilyVOHminC= 4.4VVOLmaxC=

14、0.1VVIHmin = 2.0VVILmax = 0.8V27Circuit Behavior with Resistive Loads （带电阻性负载的电路特性）Require nontrivial amounts of current to operate要求有一定的驱动电流才能工作VCCAZVCCRThevRpRnVThev +VOUTVIN28VOUT 1MRnRThevVThev +VOLmaxIOLmax29VOHminIOHmaxVCC = + 5.0VRpRn1M+If the output is HIGHVOUT = VOHminThe output is said to

15、source current. sourcing current （提供电流）IOHmax：The maximum current that the output can source in the HIGH state while still maintaining an output voltage no less than VOHmin30VOUT = 0VCC = + 5.0VRThevVThev +VIN = 1VCC = + 5.0VRThevVThev +VOUT = 1VIN = 0If the output is HIGH, the sourcing current is：I

16、f the output is LOW, the sinking current is：31Determine whether the output drive specifications of the 74LS00 over the commercial operating range are exceeded.from Table 3-4，VOHMIN=3.84V VOLMAX=0.33V IOHMAX=-4mA IOLMAX= 4mAIn the HIGH state, the gate must pull the output up to 3.84V, requiring Io=3.

17、84/1000-(5-3.84)/1000=2.68mA，is not out of spec.In the LOW state, the output pulls down to 0.33V (the maximum spec). Then the output current is Io=(5-0.33)/1000-0.33/1000=4.34mA, out of spec.VCC = + 5.0VR1=1000R2=1000VOUT32Circuit Behavior with Nonideal Inputs(非理想输入时的电路特性)VCC = + 5.0V4002.5kVIN 1.5V

18、VOUT 4.31VVCC = + 5.0V4k200VIN 3.5VVOUT 0.24V输出电压变坏（有电阻性负载时更差）更糟糕的是：输出端电流 ，功耗 33扇出（fan-out）The number of inputs that the gate can drive without exceeding its worst-case loading specifications. (在不超出其最坏情况负载规格的条件下，一个逻辑门能驱动的输入端个数。)Fanout must be examined for both possible output states, HIGH and LOW. o

19、verall fanoutmin（HIGH-state fanout，LOW-state fanout）DC fanoutAC fanout3474AHC driving 74HC LOW-State fanout：Compute the maximum fanout HIGH-State fanout：CMOS: 74AHCIOHmaxC = 50 AIOLmaxC = 50 A IIHmax = 1 A IILmax = 1 ACMOS: 74HCIOHmaxc = 20 AIOLmaxc = 20 A IIHmax = 1 A IILmax = 1 AOverall fanout：Min

20、 (HIGH-state fanout, LOW-state fanout)=50Table 3-6、3-735Effects of Loading (负载效应) 当输出负载大于它的扇出能力时输出电压变差（不符合逻辑电平的规格）传输延迟和转换时间变长温度可能升高，可靠性降低，器件失效36Unused Inputs (不用的CMOS输入端)Unused CMOS inputs should never be left unconnected (or floating).XZ1k+5VXZXZ增加了驱动信号的电容负载，使操作变慢373.6 CMOS Dynamic Electrical Behav

21、ior ( CMOS动态电气特性 ) Both the speed and the power consumption of the CMOS device depend to a large on “AC” or dynamic characteristics of the device and its load.Speed depends on two characteristics：transition time（转换时间）propagation delay（传播延迟）The amount of time that the output of a logic circuit takes

22、to change from one state to another .The amount of time that is takes for a change in the input signal to produce a change in the output signal.38Transition Time (转换时间) rise time (tr ) and fall time (tf )Fig 3-36 P.11539Transition Time (转换时间) rise time (tr ) and fall time (tf )VCC = + 5.0VRLRpRnVL+C

23、L电容两端电压不能突变在实际电路中可用时间常数近似转换时间The “on” resistances of the transistors （晶体管的“导通”电阻）stray capacitance（寄生电容）40Propagation delay（传播延迟）P.121 图3-42VINVOUTSignal path: the electrical path from a particular input signal to a particular output signal of a logic element. 41Power Consumption（功率损耗）动态功耗的来源：两个管子瞬间

24、同时导通产生的功耗 PT对负载电容充、放电所产生的功耗 PLVDD = +5.0VVOUTVINTpTnStatic Power consumption and dynamic power dissipationCL42Power Consumption（功率损耗）动态功耗的来源：两个管子瞬间同时导通产生的功耗 PT对负载电容充、放电所产生的功耗 PLStatic Power consumption and dynamic power dissipationVCC 的大小输入波形的好坏输入信号频率负载电容输入信号频率 (VCC ) 2 433.7 Other CMOS Input and Ou

25、tput Structures （其他CMOS输入输出结构）Transmission Gates 传输门When EN = 0，EN_L = 1， transistor “off ”， A and B are disconnected.When EN = 1，EN_L = 0， transistor “on ”， a low-impedance connection.双向器件传播延迟非常短可以传送模拟信号 ENEN_LAB44Schmitt-Trigger Input（施密特触发器输入）VOUTVIN5.02.12.95.0Transfer characteristicVT+VT-inputt

26、hresholdVT+VT-采用内部反馈，边沿更陡Hysteresis（滞后）：the difference between the two thresholds. Logic symbol：45波形变换Schmitt-Trigger Input（施密特触发器输入）46Device operation with slowly changing inputsSchmitt-Trigger Input（施密特触发器输入）47脉冲整形Schmitt-Trigger Input（施密特触发器输入）48Three-State Outputs （三态输出）VCCOUTENAIf EN=0， C=1, Tp

27、 off B=1, D=0, Tn off high-impedance, Hi-Z（or floating state）If EN=1， C=A , B=0 , D=A OUT=ABCDTpTnAENOUT逻辑符号49输出电平？造成逻辑混乱很大的负载电流同时流过输出级可使门电路损坏VCCAZ有源上拉active pull-upVCCB低高有源上拉的CMOS器件其输出端不能直接相联1001M1001M50特点：只能输出L态和Z态；可以外接上拉电阻实现H态；多个器件输出端可以直接连接，“线与逻辑”；Open-Drain Outputs（漏极开路输出）51Open-Drain Outputs（漏极

28、开路输出）ABZVCCVCCR pull-up resistorABZ逻辑符号希望尽量小，减少上升时间但若太小则吸收电流太大应用：驱动LED、线与、 驱动多源总线上拉电阻的计算：最大值：提供后级所需最大高电平输入电流时，能够保障输入高电平电压；最小值：输出低电平时，能够保障不超过最大输出电流；外接上拉电阻会显著降低器件转换速度； 5253ABZVCCVCCRCDVCCZ = Z1 Z2 = (AB) (CD) Z1Z2线与Open-Drain Outputs（漏极开路输出）533.10 Bipolar logicDiode 门限电压反向击穿漏电流viVTI s+RfVd正偏（导通）+反偏（截止

29、）54Diode logicABD1D2RVCCY 级联时会出现电平偏移 不能直接驱动负载 通常用于集成电路内部的逻辑单元02V LOW logic 023V undefined35V HIGH logic 1二极管与门3.10 Bipolar logic55Bipolar Junction transistor (双极结型晶体管)截止区放大区饱和区基极basecollector集电极发射极emitterVCCvo+-vi+-RBRCiCTransistor inverter56Schottky-clamped tansistor（肖特基晶体管）三极管内部电荷的建立和消散都需要时间 存储时间（

30、传输延迟的重要部分）确保晶体管正常工作时不进入深度饱和利用肖特基二极管基极集电极发射极573.10.3 Transistor-Transistor Logic (晶体管晶体管逻辑) TTL系列 低态：0.00.8V 高态：2.05.0V58Logic Families （逻辑系列）3.8 CMOS Logic FamiliesHC、HCT 高速AHC、AHCTFCT、FCT-T3.10.6 TTL familiesH高速S肖特基L低功耗（LS）A高级（AS、ALS）F快速7454FAM nn器件标号功能对称输出驱动59CMOS/TTL接口需要考虑：噪声容限、扇出、电容负载1、DC noise margingate1gate 2被驱动门驱动门低态噪声容限VNL=VILmax2- VOLmax1高态噪声容限VNH=VOHmin1- VIHmin26074HC driving 74LS HIGH state: 3.84 2.0 = 1.84V LOW state: 0.8 0.33 = 0.47V74LS driving 74HC HIGH state: 2.7 3.85 =-1.15V LOW state: 1.35 0.5 = 0.85V1、DC Noise Margi