数字系统设计与vhdl课件

1、数字系统设计第三讲 同步时序设计2提纲记分板和控制器加法器全加器行波进位加法器先行进位加法器串行加法器记分板和控制器（Score board & controller输入：递增记分INC，递减记分DEC，复位信号RESET输出：两个7段显示器具体操作：当递增输入为1，记分板上数字加1当递减输入为1，记分板上数字减1当INC和DEC同时为1，维持当前状态当RESET为1并持续5个连续周期后，记分板上记分置02数字BCD计数器2 BCD-七段数码管显示译码器abcdfegabcdgfeINCDECRESET记分板和控制器（Score board & controllerBCD=0rstcnt=0T

2、F0001rstrstcnt=4rstcnt+inc=1dec=0BCD+rstcnt=0BCD-rstcnt=0inc=0dec=0rstcnt=0s0s1TTFinc=0dec=1FTFT数字BCD计数器的ASM记分板和控制器的RTL描述记分板和控制器的RTL描述记分板和控制器的RTL描述记分板和控制器的RTL描述全加器 full adderFull_AdderSUMBACOUTCIN全加器 full adderYXSUMCOUTCINentity Full_Adder isport (A, B,CIN: in BIT; SUM, COUT: out BIT);end Half_Adder

3、;architecture Full_Adder of Full_Adder isbeginSUM = A xor B xor CIN after 15ns;COUT = (A and B) or (B and CIN) or (CIN and A) after 10ns;end Full_Adder;若一个门delay为tg,Full adders delay？32位行波加法器ripple-carry adderRipple_AdderSBACOUT CINBASUMCOUTCINFull_AdderS(1)B(1)A(1)C(1)Full_AdderS(2)B(2)A(2)C(2)Full

4、_AdderS(31)B(31)A(31)COUTFull_AdderS(0)B(0)A(0)C(0)CINSCOUTCIN行波加法器延迟？如果RCA的一个门延迟为1ns，那么32位RCA的最大工作频率是多少？32位行波加法器ripple-carry adderentity Ripple_Adder is port (A, B: in bit_vector(31 downto 0); CIN: in bit; S: out bit_vector(31 downto 0); COUT: out bit);end Ripple_Adder;architecture Ripple_Adder of

5、Ripple_Adder is component Full_Adder port(A,B,CIN: in bit; SUM, COUT: out bit); end component; signal C: bit_vector(32 downto 0);Begin C(0) = CIN; COUT = C(32); RC: for i in 31 downto 0 generate SI: Full_Adder port map (A(i), B(i), C (i), S(i), C(i+1); end generate;end Ripple_Adder;先行进位加法器Carry look

6、-ahead adder一个流行的快速加法器这个电路能在同一时间计算进位carry有2个函数：generate & propagate先行进位加法器Carry look-ahead adderci+1 = ai bi + (ai xor bi) ciGi = ai biPi = ai + bi先行进位加法器Carry look-ahead adder通过Pi和Gi计算SUM和CARRY:si = ai xor bi xor ci = ci xor Pici+1 = Gi + Pici反复使用上式得到:ci+1 = Gi + Pi(Gi-1 + Pi-1ci-1)ci+1 = Gi + PiGi

7、-1 + PiPi-1 (Gi-2 + Pi-1ci-2)4位先行进位加法器Carry look-ahead adder可见任意级的进位都可以直接计算，而无需等待进位从前面的各个级逐级传递过来任意级的进位可独立运算4位先行进位加法器Carry look-ahead adder延迟？4位先行进位加法器Carry look-ahead adderVHDL描述课本p15016位先行进位加法器Carry look-ahead adder4位CLA全加器4位CLA全加器4位CLA全加器4位CLA全加器A1512 B1512A118 B118A74 B74A30 B30S G P CS G P CS G

8、P CS G P C先行进位逻辑S3-0S7-4S11-8S15-12GG PPG3 P3 C3G2 P2 C2G1 P1 C1G0 P0C0PG=P3P2P1P0GG=G3+P3G2+P3P2G1+P3P2P1G0延迟？32位加法器的行为描述Library IEEE;Use IEEE.numeric_bit.all;Entity Adder32 is port(A,B: in unsigned (31 downto 0); Ci: in bit; - inputs S: out unsigned (31 downto 0); Co : out bit); - outputsEnd Adder

9、32;Architecture overload of Adder32 isSignal sum33: unsigned (32 downto 0);Begin Sum33 Ci); -Adder S = sum33(31 downto 0); Co O 1 0.694 0.436 a_0_IBUF (a_0_IBUF) LUT2:I0-O 1 0.086 0.000 Madd_s_lut (Madd_s_lut) MUXCY:S-O 1 0.305 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_c

10、y) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) (MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) MUXCY:CI-O 1 0.023 0.000 Madd_s_cy (Madd_s_cy) XORCY:CI-O 1 0.300 0.235 Madd_s_xor (s_31_OBUF) OBUF:I