十六进制7段数码显示译码器设计实验报告

1、实验名称：十六进制7段数码显示译码器设计实验目的：1设计七段显示译码器2.学习VerilogHDL文本文件进行逻辑设计输入；3学习设计仿真工具的使用方法；工作原理：7段数码是纯组合电路，通常的小规模专用IC,如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例如6-18作为7段译码器，输出信号LED7S的7位分别接图6-17数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g,f,e,d,c

2、,b,a分别接1,1,0,1,1,0,1；接有高电平的段发亮，于是数码管显示“5”。注意，这里没有考虑表示小数点的发光管，如果要考虑，需要增加段h,例6-18中的LED7S:0UTSTD_LOGIC_VECTOR(6DOWNTO0)应改为(了DOWNTO0)。实验内容1：将设计好的VHDL译码器程序在QuartusII上进行编辑、编译、综合、适配、仿真，给出其所有信号的时序仿真波形。实验步骤：步骤1：新建一个文件夹击打开vhdl文件；kSOP匚BuilderSystemD已wig门Filuw-AHDLFiler-EHcckD由匚归it/SchematicFile|-EDIFFileH-Stct

3、eMachineFilep-SystemVerlugHDLFile；TclScriptFile!VerilogHDLFileVHDLFileMemorHFiles：HeK-ad已匚in日IIntelForrnat)FilejMOTioryIniidlizdtionFileV已ilk：忒io门/DEbuggi门!3Filesp-In-SystemSourcesandProbesFileH-Logic.Analj-zerInterfaceFleSigialTapIILogicAnalyzerFileVectorWaveformFileS-OtherFiles|-AHDLIncludeFilek-B

4、lcckSymbolFile匚hainD已scriptionFileSyriopr1DesignCon：E：l：rainbE：File=Te:-:tFile亍OK.|Cancel步骤2：编写源程序并保存1234567831011121314151617181?2021222324252627229303132LIBRARYIEEE;USE:EET.5TD_匸DGHC_1JL4.启匸L;SENTITYDECL7SISFORT(A:ZNSID_LOGICTOR(3D0W1JTD);LED75：QUi耳亍口LOeiCVECTOR简DOWIlQQ);END；BARCHITECTURE亡OFDECL75

5、15BEPINFROCTiS(A)BEGINSCASEAISLED7SWHENr,WHENl,0QQlri=WHENr,O010ri=LED7SWHENrr020Qri=W?1ENrr0202n=WHENl,011Qri=WHENrr0112ri=WHENrr20OOri=LED7S=rr2002222ri;LED7S=rr210OllOri;LED75=rr2101101ri:LED75=rr2121101ri;LED75=riQ000111ri;LED7SLED75=rr2120112riLED75=rr2120112ri；LED75=rr2111100ri;LED75=ri0111001

6、ri;LED7575WHENrr1100ri=WHENlilCi1WHENOTHERE=LKTLL;EMDCASE;EUDPROCESS;END;步骤3：新建一个工程及进行工程设置我的文档亠我的电脑塑网上邻居.gaddertDECLTSA我的电胞圖上鄒居DECLTS,vhiWhenouclickFiriLsh,.theprojeGlwillber.createdwiththefollowirgsettings:Projecdirectory:C?/DocunrientsardSettings嘿/桌血丿Projectname:DECL75Top-leveldesignentity:DECL7SN

7、umberoffileadded:2Numberafuserlibrarivdded;0Deviceaignmert5：Familyname:CjiclorieIIID&湘已：EP3C5E144C8EDAtools:Designentry/synthesis:Simulation:/NcneTiminganalysis;dbytheF址列f*GpeaficdeviceselectedinAvaiabl$devicesislC1Othern7aShowhAvalabledeviceslistShowadvanceddevicesLHcrdCopyccrrpdtiblecnljinc/iccdnd

8、PinOptions.S3issrAConfiguratbnjnode:Gl：S3issrAConfiguratbnjnode:Gl：.=rdardJCbnfguratDondevec*U3cconFigurdtiond&vce:|EPCS4JSorfigi.-TstionDevceOptions.1C口门liguiolicndeviceI/OYokage:(AutoConfigurationscheme.liwSerialcanuseCcnfigjrationDevicelFFcrceVCCIOtoberompatiblewithGorfifli.rctionI/OydtageDual-Pu

9、rroEeFin写VoltajeFinFlscementError11mtectLanCRC|CapacLti育电Load:ng|Bo：ardTraceHodelI/OTiming&eneralConfifura.tioilFroExamninsFilesUnusedPinsSpecifylhedevceconliguralicnsckenneardtheconFigurationdevice.Note:FarHaidZopydesigis,lhescsetlirgidpptotheFPGAprotolypedevice.*Generatecarrpre?sedbit$tieam$Active

10、serialcocksource:|Description:lhemethodusedtobaddataintothedevce.Uptofoucanliguialicnsckenriesareavaiable.cfependingontheselecteddevice:PassiveSerial(PS);FastPassiveP.=rallelIFPPj.ActivePaialei(iPj申dActiveGerial|A9；L步骤4：调试程序至无误;Info:No37nchron.izerchaiastorepor七亠Warning:Atleastoneofthefiltershadsc-n

11、eproblemsandcouldnotbeiBEtched.Info:Eesi-ornisnDtfull/coEstrainedfortetuprequirenentgV-I.V亠加卜info:LC.3LJI1isHDtfull/cc-nstrainediDrholdMQUirenentsV-I.V亠加卜mro:iuarruaII64-billun.eQu.e3LluringAnalyzerwsasisuccessluioerrorsr6wamingaInfo:CuarmaIIFullOowila匸丄onwassacMsstJi0errors.11warningsnn步骤5：接着新建一个VE

12、CTORWAVEFOM文件及展出仿真波形设置1：yteni/eribgHL：LFileITclGcriplFiejj-VEfilogHDLFilel-VHDL1：yteni/eribgHL：LFileITclGcriplFiejj-VEfilogHDLFilel-VHDLFileB-MenianPiFilesHewadedmal(Intd-Formai：FiieMerrorpInitiafzationFie0-enhcatiurVDebiQginaFiles:-In-SytsmSourcejandProbesFife：LogicAnaljerInterfaceFile；Signal!apIIL

13、ogicAnalyzerFileVectorWavelorrnFileId-OtherFilesI-AHDLIncludeFilehBlockSymbolFie:-ChainDesaiptionFife:-iPopsiPisDesign匚口门过R鬥匕FieL-TextFileEndTimeTime:面Defaultewtensionoptions:Ewtensionvalue:LastclockpatternEndtimeextenszionpersignal:SignalNameDireutiun|RadixExtensionvalue匚旳_IJodeFinderlamed:厂Filter:

14、|Pins:allCustomize.ookin:|DEGL75jPInclude.subentitisL1-.1禅LZL.oMasterTimeBar:0psPoirte匚0psInterval:OpsStart:0psEnd:|01:ps2.56he5.12us7.68he10.24tle12.8us15.36竺17.92u:”iiiii1-psJIIInIIIIrnilil_jIIIII|I1:_II_II_II步骤7：设置好这个模式GariBralF血LbrariesDsmce：aOperatingSettingsandConditions自匚orrpifetbnPcicessSett

15、ing：!：3EC.AToijIGettingsB-AnasiskSynthssisSettingsiFfcterSettings3Tmiriq.naSE：SettingsAssentilerDesian.AssistantGigralTapIILogic：.Analpzsrr-Lugfc.nalvzETInterfac已g-SmulatorSettinasPovserPlar1Pow切Ana血曰Setdrgs=S5NAnalyser步骤8：生成RTL原理图步骤9：引脚锁定及源代码LIBRARYIEEE;USEIEEE.STD_L0GIC_1164.ALL;ENTITYDECL7SISPORT

16、(A:INSTD_LOGIC_VECTOR(3DOWNTO0);LED7S:0UTSTD_L0GIC_VECT0R(6DOWNTO0);END;ARCHITECTUREoneOFDECL7SISBEGINPROCESS(A)BEGINCASEAISWHEN0000=LED7S二0111111;WHEN0001=LED7S二0000110；WHEN0010=LED7S二1011011;WHEN0011=LED7S二1001111;WHEN0100=LED7S二1100110;WHEN0101=LED7S二1101101;WHEN0110=LED7S二1111101;WHEN0111=LED7S二

17、0000111;WHEN1000=LED7S二1111111;WHEN1001=LED7S二1101111;WHEN1010=LED7S二1110111;WHEN1011=LED7S二1111100;WHEN1100=LED7S二0111001;WHEN1101=LED7S二1011110;WHEN1110=LED7S二1111001;WHEN1111=LED7S二1110001;WHENOTHERS=NULL;ENDCASE;ENDPROCESS;END;n吐曲亡LxusQoiimHEFiSiCLf匹弧伽dGjrtitStrefigth盘mRa任L*列出Rput12口t2.3M1血彷.出kr

18、J-匸A2lJCEATKL1X.s/I4efwjri；沁(ccfaulE.斗z処1_input!CEJU-iL1(dahJfj5ULED用6OjhjIIC&W：33a.5(deFffjH：LBZi带呱巾肚圖6utpiil1UCMV.3J2.3ii(defkiC-LBD75a.0-SnA(oefaJiEfoefdi収;-LED75HDuiput-2.SW血虹旳Lm?S6.03rrA虚bdl)ia)75jOuqhJIIO6WIK：J亦如越LBJ為顶口9皿LED肝RjipulICCANKJmijd皀Fb-巾LBD75fl.0SZ肚fed1：1O3MED陌2U(JefwJI-LEDraft.0SmAc

19、efajlfLI2耳西0dbqhJllO&w：32.5RLEDKfi.qfA(ckihUi；-12*”刖nod。实验内容二：1、硬件测试。程序不一样，其他步骤相同操作LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT4BISPORT(CLK,RST,ENA:INSTD_LOGIC;OUTY:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);ENDCNT4B;ARCHITECTUREbehavOFCNT4BISBEGINPROCESS(CLK

20、,RST,ENA)VARIABLEQ:STD_LOGIC_VECTOR(3DOWNTO0);BEGINIFRST=0THENQ:=(OTHERS=0);ELSIFCLKEVENTANDCLK=1THENIFENA=1THENQ:=Q+1;ENDIF;ENDIF;IFQ=1111THENCOUT=1;ELSECOUT=0;ENDIF;OUTYclockO,RST=rstO,ENA=enaO,OUTY=tmp,COUT=coutO);u2:DECL7SPORTMAP(A=tmp,q=led);ENDARCHITECTUREadl;SiiriulationWaveformsEinnlooimode：

21、Fiuwtiorsil临MasterTheBarA,Z-|A10zLockD射SiiriulationWaveformsEinnlooimode：Fiuwtiorsil临MasterTheBarA,Z-|A10zLockD射由口血r=+0coutJOA-kd.口；口XI-15.425nsJjJFalter:30.0Z7.CEnsIrtEC/dt11.6nsStart10.0nsEndJL3P厂启畫厂戏t6Y6J心一yy：-y;(：、LMmi-a&XX打3、RTL原理图：（计数器和译码器连接电路的顶层文件原理图）CMT4S：u1ClOCkQICMT4S：u1ClOCkQIenaO|rstOIENAOLTTYp.jqECL7S：u2ed6.acoutO注意：运用实验三，调用实验一和实验二的RTl原理图得计数器和译码器连接电路的顶层文件原理图在引脚锁定及硬件测试。建议选GW48系统的