FPGA中用定制ROM产生正弦信号

1、FPGA中用定制ROM产生正弦信号简介：本文详细介绍了在fpga中定制ROM,以及用查表法产生正弦波的方法，并借助matlab加以验证。编译软件用xilinx13.1.1.借助matlab生成ISE中ROM的.coe文件。在matlab工作区中输入以下代码。fid=fopen(sin.txt,a);str1=MEMORY_INITIALIZATION_RADIX=10;str2=MEMORY_INITIALIZATION_VECTOR=;fprintf(fid,t%snt%sn,str1,str2);fork=1:256;y(k)=sin(2*pi*k/256);y(k)=int8(y(k)*

2、100);fprintf(fid,t%4.0ft%cn,y(k),);endlileEditText21fclose(fid);在work文件夹下回生成一个sin.txt的文件，；打开ISE。2.在ISE中建立newproject添加新的verilogmodule文件，直接点next直MEMORY.MEMORYSelectSonrceTypeSelectsourcetypefileIP(COREGenerator&Arc!OjSchematiceJUserDocu/nent7VerilogModuleV1VerilogTestFixture10SelectSoxirceTypeSelectso

3、urcetypefil/.ImplementatimnConstrai丿J丿呂又攵:寸coe,IF(COREGenerator敕ArchitectujMEMFileSchematicUserDocumentVerilogModuleVerilogTestFixture；.:FIFOsMemoryInterfaceGenerators疗RAM客&KOMsBlockMemoryDistributedMemoryGeiver0止-_%t%*E点击next-finishMemoryTypeSinglePortROIZiDDRA3:D$BITERR-nDeiTERRROADDRECCpDRS7ACLKA

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6、antiationTemp；JoelIPSymbolRegisterPortAOutputRegisterPortAinputADDRA70DOUTA|15:0)3930314142sinromyour_inst.(lka(clka)/inputc：/AdditionalCoinments:/zmodulecounter(en3930314142sinromyour_inst.(lka(clka)/inputc：/AdditionalCoinments:/zmodulecounter(enzell1-了relsec=0;endelsec=0;W%.1countercO(enzclkzacBeg

7、inCuthProcesses:mysinromoutmyromromO(,clka(elk)i/input.addrafaddra)/iiAlDesignSummary/ReportsDesignUtilitiesUserConstraints空dhw-芒-疫:工ViewRTLSchematicViewTechnologySchematicCheckSyntaxA*i4匕PA+VbA亡*.顶层示意图以及内部模块连接*LUc(7;0加仿cOmysinrcDesignBehaviorH添加ITSelectSourceTypeSelectsourcetype,filen泗电anditslocati

8、on.Aksoci顶层示意图以及内部模块连接*LUc(7;0加仿cOmysinrcDesignBehaviorH添加ITSelectSourceTypeSelectsourcetype,filen泗电anditslocation.AksociateSourceSelectasource时ithwhichtoassociatethenewsource.阳BMMFileChipScopeDefinitionandConnectionFile舉ImplementtionConstr乱int玄File“IF(COREGenerator&ArchitectureWizard)MEMFilemysiiuromcounterninrommysinroimysircounter添加代码:noduletest;en(en)zel