at89c52单片机中英文资料对照外文翻译文献综述

1、 at89c52 单片机中英文资料对照外文翻译文献综述at89c52 单片机简介中英文资料对照外文翻译文献综述AT89C52 Single-chip microprocessor introductionSelection of Single-chip microprocessor1. Development of Single-chip microprocessorThe main component part of Single-chip microprocessor as a result of by suchcentralize to be living to obtain on th

2、e chip ，In immediate future middle processorCPU。Storage RAM immediatelymemoy read ROMInterrupt system、Timer /scounter along with I/Os rim electric circuit awaits the main microcomputer section ，The lumping is living on the chip。Although the Single-chip microprocessor r is only achip，Yet through make

3、s up and the meritorous service be able to on sees，It hadhaveed the calculating machine system property，calling it for this reason act asSingle-chip microprocessor r minisize calculating machine SCMS and abbreviate theSingle-chip microprocessor。1976Year the Inter corporation put out 8 MCS48Set Singl

4、e-chip microprocessorcomputer，After being living more than 20 years time in development that obtaincontinuously and wide-ranging application。1980Year that corporation put out high at89c52 单片机中英文资料对照外文翻译文献综述performance MCS 51Set Single-chip microprocessor。This type of Single-chipmicroprocessor merito

5、rous service capacity、The addressing range wholly than earlyphase lift somewhat，Use also comparatively far more at the moment。1982Year thatcorporation put out the taller 16 Single-chip microprocessor MCS of performance oncemore 96Set。The Single-chip microprocessor computer development havees theperf

6、ormance more and more to be improved More and more distinguishings feature ofstrain。2. Adopt the Single-chip microprocessor strong pointHacker use，Agileization of application。 Have memory、Calculation and look-up meritorous service capacity。May make theapparatus bearing that the rule can not make。 Th

7、e command system is fit for the real-time contro。l Bulk is little，Execution speed is quickly。 Dependability is high，The antijamming capability is powerfu。l The temperature use limit is vas。t Power-off protection is improved。 The product development cycle brief。 Identical set is much as the necessary

8、 interface chip sor，t The meritorous service beable to be completely，Be convenient for to pick up achieve the minimal system。 On the basis of the tall science and technology demand，Integration in common usesoftware，Hardware （In case PL/M language，DAMs wave pattern producer，Analogswitch awaits ）Appli

9、cation is agile。Hence，Native is designed adoping with the Single-chip microprocessor corecomponents designs。3 . AT89C52 ComponentAT89C52 microprocessor main function parameter：And completely compatible with the MCS-51 product instruction and thepin at89c52单片机中英文资料对照外文翻译文献综述The 8K byte is programmabl

10、e/scratches writes Flash to dodge the fastmemory1,000 time scratches writes the cycleEntire static operation: 0Hz - 24MHzThree levels of encryptions program memory2568 byte interior RAMs32 programmable I/O lines3 16 fixed time/counters8 interrupt sourcesProgrammable serial UART channelThe low power

11、loss is idle and falls the electricity patternCPUs compositionThe CPU is the Single-chip microprocessor core components，It consists of thatruing the arithmetic sum controller awai。t1. Arithmetic unitThe meritorous service of arithmetic unit be able to be carrying on arithmeticoperation and logic ope

12、ration，The half-byte may be adjustThe separate word lengthand so on the data manipulate。2. Order counter PCIt is used for leaving second order which will the be carried out addres。s The addressthat the order points out in accordance PC brings out through the storage afterward，s ThePC be able to plus

13、 1 voluntarily，In immediate future point to the second orde。r3. Order product registerLeave the instruction code in the order register 。When CPUs executeinstruction，Send into the order register through reading aloud the instruction code getin the order storage，Decipher queen after the decipherer ，Is

14、sue the relevant controlsignal through fixed time against the control circuit 。Complete the order meritorousservice capacity. at89c52 单片机中英文资料对照外文翻译文献综述Storage1. Order storageUsed to leave order and form constant。As to 8751 ，EA1Hour，Slice internalprocedure storage is occupied 0000H 0When FFFH，Order

15、storage fetch piece throughthe slice.2. Data storage utensil8751No matter the Single-chip microprocessor data storage utensil is living on thephysics and the logic goes up wholly being divided into two addresss space，One act asthe internal data storage，Call on the internal data storage in the way of

16、 order of MOV，sAnother act as the external data storage utensil，Call on external data storage articles ofdaily use order of MOVXs，Addressing mode indirect addressing。Meritorous service capacity register special.MCS51Latch inner place the Single-chip microprocessor 、Timer、Serial portdata bumpers alon

17、g with different control register and the conditions register haswholly ariseed with the meritorous service capacity register special shape。TAMsaddress space limit included they decentralized distribution（s 80HFDH）It is inside。8751The inside particular meritorous service capacity register consists o

18、foperating the register、Register of address、The rim latch reaches to be used theinterception、Count / fixed a time and the serial port administration register。The calculation register consists of accumulator A、Register B and program modeword register PSW。The register of address consists of indicator

19、DPTR of warehouse indicator SPand data addresses 。MCS51The SP of Single-chip microprocessor act as 8，Theplace included the warehouse among the RAM is comparatively more agile。Datapointer DPTR is 16 registers，Such high position byte is expressed in the way of DPh，The position is expressed in the way

20、of DPI ，In immediate future may as 16 registerDPTRs the handle， 8 register DPh and DPIs who also may do worthwhile at89c52 单片机中英文资料对照外文翻译文献综述independence handle。Port P0 The P3 is separately I/O port P0 The latch of P3。P0P3 is asregister special still usable direct addressing means participation else

21、 operatinginstruction operation。Serial data bumper SBUF is used conveying either the data the receiveedloading，In reality it is consising of two independence registers，One is transmiting thebumper，Another is receives the bumper。AT89C52 pin explanationThe AT89C52 monolithic integrated circuit uses 40

22、 pins the double row straighttoinsert the seal way.The power source pin turns on the monolithic integrated circuit thework powersource.VCC: Meets the +5V power source.GND: Earth. Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port,each pin can sink eight TTL inputs. When

23、 1s are written to port 0 pins, the pins can beused as highimpedance inputs.Port 0 can also be configured to be the multiplexed loworder address/data busduring accesses to external program and data memory. In this mode, P0 has internalpullups.Port 0 also receives the code bytes during Flash programm

24、ing and outputs thecode bytes during program verification. External pullups are required during programverification. Port 1:Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, theyare pulled hig

25、h by the internal pullups and can be used as inputs. As inputs,Port 1 pins that at89c52 单片机中英文资料对照外文翻译文献综述are externally being pulled low will source current (IIL) because of the internal pullups.In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 externalcount input (P1.0/T2) and

26、 the timer/counter 2 trigger input (P1.1/T2EX), respectively,as shown in the following table.Port 1 also receives the low-order address bytes during Flash programming andverification. Port 2:Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2output buffers can sink/source fou

27、r TTL inputs.When 1s are written to Port 2 pins, theyare pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins thatare externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from ext

28、ernal programmemory and during accesses to external data memory that use 16-bit addresses(MOVX DPTR). In this application, Port 2 uses strong internal pullups whenemitting 1s. During accesses to external data memory that use 8-bit addresses(MOVX RI), Port 2 emits the contents of the P2 Special Funct

29、ion Register.Port 2 also receives the high-order address bits and some control signals duringFlash programming and verification. Port 3:Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins, theyar

30、e pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins thatare externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51, asshown in the following table.Port 3 also receives

31、 some control signals for Flash programming and verification. RST:Reset input. A high on this pin for two machine cycles while the oscillatoris running resets the device ALE/PROG:Address Latch Enable is an output pulse for latching the low byte of at89c52 单片机中英文资料对照外文翻译文献综述the address during accesse

32、s to external memory.This pin is also the program pulse input(PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillatorfrequency and may be used for external timing or clocking purposes. Note, however,that one ALE pulse is skipped during each access

33、to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH.With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise,the pin is weakly pulled high. Setting the ALE-disable bit has no effect if themicrocontroller is in external execu

34、tion mode. PSEN:Program Store Enable is the read strobe to external program memory.When the AT89C52 is executing code from external program memory, PSEN isactivated twice each machine cycle, except that two PSEN activations are skippedduring each access to external data memory. EA/VPP:External Acces

35、s Enable. EA must be strapped to GND in order toenable the device to fetch code from external program memory locations starting at0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will beinternally latched on reset.EA should be strapped to VCC for internal program executions.This

36、 pin also receives the 12-volt programming enable voltage (VPP) duringFlash programming when 12-volt programming is selected. XTAL1:Input to the inverting oscillator amplifier and input to the internal clockoperating circuit. XTAL2:Output from the inverting oscillator amplifier. Special Function Reg

37、isters:A map of the on-chip memory area called the SpecialFunction Register (SFR) space is shown in Table 1.Note that not all of the addresses are occupied,and unoccupied addresses may notbe implemented on the chip.Read accesses to these addresses will in general return at89c52 单片机中英文资料对照外文翻译文献综述ran

38、dom data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted locations,since they may beused in future products to invoke new features. In that case, the reset or inactivevalues of the new bits will always be 0.Data Memory:The AT89C52 implements

39、256 bytes of on-chip RAM. The upper128 bytes occupy a parallel address space to the Special Function Registers. That meansthe upper 128 bytes have the same addresses as the SFR space but are physically separatefrom SFR space.When an instruction accesses an internal location above address 7FH, the ad

40、dressmode used in the instruction specifies whether the CPU accesses the upper 128 bytesof RAM or the SFR space. Instructions that use direct addressing access SFR space.Timer 0 and 1:Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0and Timer 1 in the AT89C51.Timer 2:Timer 2 is a 16

41、-bit Timer/Counter that can operate as either a timer or anevent counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown inTable 2).Timer 2 has three operating modes: capture, auto-reload (up or down counting),and baud rate generator. The modes are selected by bits in T2CON, a

42、s shown in Table 3.Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, theTL2 register is incremented every machine cycle. Since a machine cycle consists of12 oscillator periods, the count rate is 1/12 of the oscillator frequency.In the Counter function, the register is incr

43、emented in response to a 1-to-0transition at its corresponding external input pin, T2. In this function, the externalinput is sampled during S5P2 of every machine cycle. When the samples show a highin one cycle and a low in the next cycle, the count is incremented. The new countvalue appears in the

44、register during S3P1 of the cycle following the one in which thetransition was detected. Since two machine cycles (24 oscillator periods) are requiredto recognize a 1-to-0 transition,the maximum count rate is 1/24 of the oscillator at89c52 单片机中英文资料对照外文翻译文献综述frequency. To ensure that a given level is

45、 sampled at least once before it changes, thelevel should be held for at least one full machine cycle.AT89C52 单片机介绍1. 单片机的发展单片机因将其主要组成部分集中在一个芯片上得名，即中央处理器CPU。存储器 RAM只读存储器 ROM中断系统定时器/计数器以及 I/O 口电路等主要微型机部分，集中在一个芯片上。虽然单片机只是一个芯片，但从组成和功能上看，它已具有了计算机系统的属性，为此称它为单片机微型计算机SCMS 简称单片机。1976 年 Inter 公司推出了 8 位的 MCS4

46、8 系列单片机，在以后 20 多年的时间里得到了不断的发展和广泛的应用。1980 年该公司推出了高性能的MCS51 系列单片机。这类单片机的功能寻址范围都比早期有所提高，目前应用也比较多。1982年该公司又推出了性能更高的16 位单片机 MCS96 系列的。单片机发展具有性能越来越完善品种越来越多的特点。2. 采用单片机的优点 硬件通用化，应用灵活化。 具有记忆计算和查表功能。可制成常规无法制成的仪器仪表。 指令系统适合实时控制。 体积小，执行速度快。 可靠性高，抗干扰能力强。 温度使用范围广。 断电保护完善。 产品开发周期短。 同一系列和配套接口芯片种类多，功能全，便于挑选来实现最小系统。

47、根据高科技要求，集成常用软件，硬件（如 PL/M,BASIC,FORTH 语言，DAM波形发生器，模拟开关等）应用灵活。因此，本设计采用以单片机位核心的部件设计。 at89c52单片机中英文资料对照外文翻译文献综述3. AT89C52 单片机的结构AT89C52 单片机主要性能参数： 与 MCS-51 产品指令和引脚完全兼容 8K 字节可编程/擦写 Flash 闪速存储器 1000 次擦写周期 全静态操作：0Hz24MHz 三级加密程序存储器 2568 字节内部 RAM 32 个可编程 I/O 口线 3 个 16 位定时/计数器 8 个中断源 可编程串行 UART 通道低功耗空闲和掉电模式3.

48、1 CPU 结构CPU 是单片机的核心部件，它由运行算术和控制器等组成。1. 运算器运算器的功能是进行算术运算和逻辑运算，可以对半字节单字节等数据进行操作。2. 程序计数器 PC它用来存放下一条要执行的指令的地址。当一条指令按照PC 所指的地址从存储器中取出后，PC 会自动加 1，即指向下一条指令。（3）指令积寄存器指令寄存器中存放指令代码。CPU 执行指令时，由程序存储器中读取的指令代码送入指令寄存器，经译码器译码后，由定时与控制电路发出相应的控制信号。完成指令功能。3.2 存储器1. 程序存储器用于存放程序及表格常数。对于 8751，EA1 时，片内程序存储器占用 0000H0FFFH 时

49、，则从片外程序存储器取指令。2. 数据存储器8751 单片机数据存储器无论在物理上和逻辑上都分为两地址空间，一个为内部数据存储器，访问内部数据存储器用MOV 指令，另一个为外部数据存储器，访问外部数据存储器用 MOVX 指令，寻址方式间接寻址。3.3 专用功能寄存器MCS51 单片机内的锁存器、定时器、串行口数据缓冲器以及各种控制寄存器和状态寄存器都是以专用功能寄存器的形式出现的。它们分散的分布在内部TAM 地址空间范围（80HFDH）内。8751 内的特殊功能寄存器包括运算寄存器、地址寄存器、口锁存器及用于中断、计数/定时和串行口管理的寄存器。 at89c52单片机中英文资料对照外文翻译文献

50、综述运算寄存器包括累加器 A寄存器 B 及程序状态字寄存器 PSW。地址寄存器包括堆栈指示器SP 和数据地址指示器 DPTR。MCS51 单片机的 SP为 8 位，堆栈在内部 RAM 中的位置比较灵活。数据指针DPTR 是一个 16 位寄存器，其高位字节用 DPh 表示，地位用 DPI 表示，即可以作为一个16 位寄存器 DPTR 来处理，也可以作为独立的8 位寄存器 DPh 和 DPI 处理。端口 P0P3 分别是 I/O 端口 P0P3 的锁存器。P0P3 作为专用寄存器还可用直接寻址方式参与其他操作指令。串行数据缓冲器 SBUF 用于传送或接受的数据的存放，它实际上是由两个独立的寄存器组

51、成，一个是发送缓冲器，另一个是接收缓冲器。3.4 AT89C52 引脚说明AT89C52 单片机采用 40 引脚的双列直插封装方式。电源引脚接入单片机的工作电源。VCC：接+5V 电源。GND：接地。 P0 口：P0 口是一组 8 位漏极开路型双向I/O 口，也即地址/数据总线复用口。作为输出口用时，每位能吸收电流的方式驱动8 个 TTL 逻辑门电路，对端口P0写“1”时，可作为高阻抗输入端用。在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8 位）和数据总线复用，在访问期间激活内部上拉电阻。在 Flash 编程时，P0 口接受指令字节，而在程序校验时，输出指令字节，校验时，要求外

52、接上拉电阻。 P1 口：P1 是一个带内部上拉电阻的8 位双向 I/O 口，P1 的输出缓冲级可驱动（吸收或输出电流）4 个 TTL 逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流。与 AT89C51 不同之处是，P1.0 和 P1.1 还可分别作为定时/计数器 2 的外部计数输入（P1.0/T2）和输出（P1.1/T2EX），Flash 编程和程序校验期间，P1 接收低 8 位地址。 P2 口：P2 是一个带有内部上拉电阻的8 位双向 I/O 口，P2 的输出缓冲级可驱动（吸收或输出

53、电流）4 个 TTL 逻辑门电路。对P2 端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流。在访问外部程序存储器或 16 位地址的 外部数据存储器时，P2 口送出高8 位地址数据。在访问8 位地址的外部数据存储器时，P2 口输出 P2 锁存器的内容。Flash 编程或校验时，P2 亦接收高位地址和一些控制信号。 P3 口：P3 是一个带有内部上拉电阻的8 位双向 I/O 口，P3 的输出缓冲级可驱动（吸收或输出电流）4 个 TTL 逻辑门电路。对P3 端口写“1”，它们被内部上拉电阻拉高并可作为输入端口。此时，被外部拉低的P3 口将用上拉电