北航电子电路设计数字部分实验报告

1、第14页 共14页北航电子电路设计数字局部实验报告电子电路设计数字局部实验报告 学 院： 姓名： 实验一 简单组合逻辑设计 实验内容 描绘一个可综合的数据比拟器，比拟数据a 、b的大小，假设一样，那么给出结果1，否那么给出结果0。 实验仿真结果 实验代码 主程序 module pare(equal,a,b); input7:0 a,b; output equal; assign equal=(ab)?1:0; endmodule 测试程序 module t; reg7:0 a,b; reg clock,k; wire equal; initial begin a=0; b=0; clock=0

2、; k=0; end always #50 clock = clock; always (posedge clock) begin a0=$random%2; a1=$random%2; a2=$random%2; a3=$random%2; a4=$random%2; a5=$random%2; a6=$random%2; a7=$random%2; b0=$random%2; b1=$random%2; b2=$random%2; b3=$random%2; b4=$random%2; b5=$random%2; b6=$random%2; b7=$random%2; end initia

3、l begin #100000 $stop;end pare m(.equal(equal),.a(a),.b(b); endmodule 实验二 简单分频时序逻辑电路的设计 实验内容 用always块和(posedge clk)或(negedge clk)的构造表述一个1/2分频器的可综合模型，观察时序仿真结果。 实验仿真结果 实验代码 主程序 module fdivision(RESET,F10M,out); input F10M,RESET; output out; reg out; reg7:0 i; always (posedge F10M) if(!RESET) begin out

4、=0; i=0; end else if(i=2|i=3) begin out=out; i=i+1; end else if(i=5) i=1; else i=i+1; endmodule 测试程序 timescale 1ns/100ps module division_top; reg F10M,RESET; wire out; always #50 F10M=F10M; initial begin RESET=1; F10M=0; #90 RESET=0; #100 RESET=1; #10000 $stop; end fdivision fdivision(.RESET(RESET),

5、.F10M(F10M),.out(out); endmodule 实验四 阻塞赋值与非阻塞赋值的区别 实验内容 比拟四种不同的写法，观察阻塞与非阻塞赋值的区别。 Blocking： always (posedge clk) begin b=a; c=b; end Blocking1： always (posedge clk) begin c=b; b=a; end Blocking2： always (posedge clk) b=a; always (posedge clk) c=b; non_Blocking： always(posedge clk) begin b=a; c=b; End

6、 实验仿真结果 实验代码 主程序 module blocking(clk,a,b,c); output3:0 b,c; input3:0 a; input clk; reg3:0 b,c; always (posedge clk) begin b=a; c=b; end endmodule 测试局部 timescale 1 ns/100 ps include “./blocking.v“ include “./blocking1.v“ include “./blocking2.v“ include “./non_blocking.v“ module pareTop; wire3:0b11,c1

7、1,b12,c12,b13,c13,b2,c2; reg3:0a; reg clk; initial begin clk=0; forever#50 clk=clk; end initial begin a=4h3; $display(“%d“,a); #100 a=4h7; $display(“%d“,a); #100 a=4hf; $display(“%d“,a); #100 a=4ha; $display(“%d“,a); #100 a=4h2; $display(“%d“,a); #100 $stop; end blocking blocking(clk,a,b11,c11); blo

8、cking1 blocking1(clk,a,b12,c12); blocking2 blocking2(clk,a,b13,c13); non_blocking non_blocking(clk,a,b2,c2); endmodule 实验五 用always块实现较复杂的组合逻辑 实验目的 运用always块设计一个8路数据选择器。要求：每路输入数据与输出数据均为4位2进制数，中选择开关至少3位或输入数据发生变化时，输出数据也相应地变化。 实验仿真结果 实验代码 主程序 module alu(out,opcode,a1,a2,a3,a4,a5,a6,a7,a8); output3:0 out

9、; reg3:0 out; input3:0 a0,a1,a2,a3,a4,a5,a6,a7; input2:0 opcode; always(opcode or a1 or a2 or a3 or a4 or a5 or a6 or a7 or a0) begin case(opcode) 3d0: out=a0; 3d1: out=a1; 3d2: out=a2; 3d3: out=a3; 3d4: out=a4; 3d5: out=a5; 3d6: out=a6; 3d7: out=a7; default:out=4b0000; endcase end endmodule 测试程序 ti

10、mescale 1ns/1ns include “./main5.v“ module alutext; wire3:0 out; reg3:0 a1,a2,a3,a4,a5,a6,a7,a8; reg2:0 opcode; initial begin a1=$random%16; a2=$random%16; a3=$random%16; a4=$random%16; a5=$random%16; a6=$random%16; a7=$random%16; a8=$random%16; repeat(100) begin #100 opcode=$random%8; a1=$random%16

11、; a2=$random%16; a3=$random%16; a4=$random%16; a5=$random%16; a6=$random%16; a7=$random%16; a8=$random%16; end #100 $stop; end alu alu(out,opcode,a1,a2,a3,a4,a5,a6,a7,a8); endmodule 实验六 在 Verilog HDL中使用函数 实验目的 设计一个带控制端的逻辑运算电路，分别完成正整数的平方、立方和最大数为5的阶乘运算。 第二种，假设8位数据是按照时钟节拍串行输入的，要求用时钟触发任务的执行法，每个时钟周期完成一次数

12、据交换操作。 任务1：做出如上逻辑电路设计并仿真； 任务2：考虑去抖情况，对于感应信号到达存在毛刺(小于0.5s)，设计适宜逻辑并剔出。 任务3：假设为节约能，下一个灯点亮的同时将自动关闭上一个灯，做出如上逻辑设计并仿真仅考虑一个人的情况 实验仿真结果 实验代码 主程序 module light_All(clk10,rst,switch,light); input clk10,rst; input2:0switch; output2:0light; reg2:0state1,state2,state3; reg7:0count1,count2,count3; reg2:0count_1,cou

13、nt_2,count_3; reg2:0light; parameter state1_start=3b000,state2_start=3b000,state3_start=3b000, state1_work=3b001,state2_work=3b001,state3_work=3b001, state1_up=3b010,state2_up=3b010,state3_up=3b010, state1_down=3b011,state2_down=3b011,state3_down=3b011, state1_other=3b100,state2_other=3b100,state3_o

14、ther=3b100; always(posedge clk10) if(!rst) begin state1=state1_start; count1=8b0; count_1=3b0; end else if(switch0=b1-count_14) count_1=count_1+1; else case(state1) state1_start: if(switch0=b1) begin state1=state1_up; count1=78; end else begin state1=state1_start; light0=b0; end state1_work: if(coun

15、t10) begin count1=count1-1; if(switch0=b0-(state2=3b010|state3=3b010) begin light0=b0; state1=state1_down; end end else if(switch0=b0) begin state1=state1_down; end else begin state1=state1_other; count1=39; end state1_other: if(switch0=b1) state1=state1_other; else if(count10) begin count1=count1-1

16、; if(switch0=b0-(state2=3b010|state3=3b010) begin light0=b0; state1=state1_down; end end else state1=state1_down; state1_down: begin light0=b0; count_1=3b0; state1=state1_start; end state1_up: begin light0=b1; state1=state1_work; end default: state1=state1_start; endcase always(posedge clk10) if(!rs

17、t) begin state2=state2_start; count2=8b0; count_2=3b0; end else if(switch1=b1-count_24) count_2=count_2+1; else case(state2) state2_start: if(switch1=b1) begin state2=state2_up; count2=78; end else begin state2=state2_start; light1=b0; end state2_work: if(count20) begin count2=count2-1; if(switch1=b

18、0-(state1=3b010|state3=3b010) begin light1=b0; state2=state2_down; end end else if(switch1=b0) begin state2=state2_down; end else begin state2=state2_other; count2=39; end state2_other: if(switch1=b1) state2=state2_other; else if(count20) begin count2=count2-1; if(switch1=b0-(state1=3b010|state3=3b0

19、10) begin light1=b0; state2=state2_down; end end else state2=state2_down; state2_down: begin light1=b0; count_2=3b0; state2=state2_start; end state2_up: begin light1=b1; state2=state2_work; end default: state2=state2_start; endcase always(posedge clk10) if(!rst) begin state3=state3_start; count3=8b0

20、; count_3=3b0; end else if(switch2=b1-count_34) count_3=count_3+1; else case(state3) state3_start: if(switch2=b1) begin state3=state3_up; count3=78; end else begin state3=state3_start; light2=b0; end state3_work: if(count30) begin count3=count3-1; if(switch2=b0-(state1=3b010|state2=3b010) begin ligh

21、t2=b0; state3=state3_down; end end else if(switch2=b0) begin state3=state3_down; end else begin state3=state3_other; count3=39; end state3_other: if(switch2=b1) state3=state3_other; else if(count30) begin count3=count3-1; if(switch2=b0-(state1=3b010|state2=3b010) begin light2=b0; state3=state3_down;

22、 end end else state3=state3_down; state3_down: begin light2=b0; count_3=3b0; state3=state3_start; end state3_up: begin light2=b1; state3=state3_work; end default: state3=state3_start; endcase endmodule 测试程序 timescale 100ns/10ns module test_light_All; reg clk10,rst; reg2:0 up,down; wire2:0 swh; wire2

23、:0 light; parameter HALF_PERIOD = 5; always #HALF_PERIOD clk10=clk10; initial begin clk10 = 0; rst = 1; up = 3b000;down = 3b000; #1 rst = 0; #10 rst = 1; #100 up = 3b001; down = 3b000; #500 up = 3b010; down = 3b100; #600 up = 3b011; down = 3b010; #30 up = 3b010; #80 up = 3b011; #900 up = 3b010; down = 3b001; #500 up = 3b; down