初级数字ic设计工程师网课-作业与

Topicsuvm_sequence_itemuvm_sequence_item

methodstestcase

with

modified

sequence

itemset_type_override_by_typeset_inst_override_by_type2016/11/27项目经验上E教

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2e没课网专业集成电路What

is

transaction?Networking

transactionsTCP/IPWIFI3G/4GBus

transactionsAMBA-AHB/APB/AXIPCI/PCI-ESATAUSBSDInstructionsX86ARM2016/11/27项目经验上E教

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3e没课网专业集成电路UVM

Transaction

FlowsequencerdriverScorsequencerDrivertestcaseDUTmonitormonitorCreatestimulusDrive

andfreeAccumulatecollect2016/11/27项目经验上E教

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4e没课网专业集成电路UVM

modeling

transactionDerived

from

uvm_sequence_item

base

classBuilt-in

support

for

stimulus

creation,

printing,

comparing,

etc.Properties

should

be

public

by

defaultMust

be

visible

to

constraints

in

other

classesProperties

should

be

rand

by

defaultCan

be

turned

off

with

rand_modeclass

transaction

extends

uvm_sequence_item;rand

bit

[31:0]

sa,

da;randbit

[15:0]len;randbit

[7:0]payload[$];randbit

[31:0]fcs;function

new

(stringname

=

“transaction”);super.new

(name);this.fcs.rand_mode

(0);endfunctionendclass：transaction2016/11/27项目经验上E教

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consideration

1/2Embed

transaction

descriptorComponent

interprets

transaction

to

executeclass

cpu_tr

extends

uvm_sequence_item;typedef

enum

{READ,

WRITE}

kind_t;rand

int

delay=0;rand

kind_t

kind;rand

bit

[31:0]

addr,

data;function

new

(string

name=“cpu_tr”);super.new

(name);this.delay.rand_mode(0);endfunctionendclassclass

cpu_driver

extend

uvm_driver

#

(cpu_t

r);task

execute

(cpu_tr

tr);repeat(tr.delay)

@

(sigs.drv_clk);case

(tr.kind)

begincpu_tr::READ:tr.data

=

this.read(tr.addr);cpu_tr::WRITE:this.write

(tr.addr,

tr.data);endendtaskendclass2016/11/27项目经验上E教

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6e没课网专业集成电路Properties

consideration

2/2Embed

transaction

status

flagSet

bycomponent

for

executionstatusclass

cpu_tr

extends

uvm_sequence_item;typedef

enum

{IS_OK,

ERROR}

status_t;rand

status_t

status=IS_OK;…function

new

(string

name=“cpu_tr”);super.new

(name);this.status.rand_mode(0);endfunctionendclassclass

cpu_driver

extend

uvm_driver

#

(cpu_tr);task

execute

(cpu_tr

tr);repeat(tr.delay)

@

(sigs.drv_clk);case

(tr.kind)

…

endcaseif

(error_condition_encountered)tr.status

=

cpu_tr::ERROR;`uvm_info(“DEBUG”,

tr.sprint(),UVM_HIGH)endtaskendclass2016/11/27项目经验上E教

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7e没课网专业集成电路Transactions:

Must-Obey

ConstraintsDefine

constraint

block

for

the

must-obey

constraintsNever

turned

offNever

overriddenName

“class_name_valid”ExampleNon-negative

values

for

int

propertiesCorrelation

between

embedded

array

size

and

a

size

propertyclass

transaction

extends

uvm_sequence_item;rand

int

len;rand logic

[31:0]

payload

[$];…constraint

transaction_valid

{len

>0;payload.size() inside

{[10:60]};}endclass2016/11/27项目经验上E教

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8e没课网专业集成电路Transactions:

Should-Obey

ConstraintsDefine

constraint

block

for

should-obey

constraintsCan

be

turned

off

to

inject

errorsOne

block

per

relationship

setCan

be

individually

turned

off

or

overloadedName

“class_name_rule”class

transaction

extends

uvm_sequence_item;…constraint

sa_rule

{sa

[41:40]

==

2`b00;}constraint

ieee_rule

{len

in

{46:1500};data.size()

==

len;}…constraint

fcs_rule

{fcs

==

32’h0000_0000;}endclass2016/11/27项目经验上E教

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9e没课网专业集成电路Transactions:

Constraint

ConsiderationsCan’t

accidentally

violate

valid

constraintsConstraint

solver

will

fail

if

the

user

constraintsconstraintswith

valid2016/11/27项目经验上E教

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1e没课网专业集成电路uvm_sequence_item

class

tree

uvm_object

get_name()get_full_name()get_type()clone()copy()print()sprint()compare()pack()unpack()record()uvm_sequence_itemset_item_context()set_transaction_id()get_transaction_id()set_sequence_id()get_sequence_id()set_id_info()set_sequencer()get_sequencer()set_parent_sequence()get_parent_sequence()2016/11/2711o

mTransaction

class

methodsDefault

base

class

methodMethods

create

by

macrosvirtual

function

uvm_object

clone();virtual

function

void

print

(uvm_printer printer

=

null);virtual

function

string

sprint

(uvm_printer

printer

=

null);virtual

function

void

copy

(uvm_object

rhs);virtual

function

bit

compare

(uvm_object

rhs,

parercomparer=null);virtual

function

int

pack

(ref

bit

bitstream[],

input

uvm_packerpacker=null);virtual

function

int

unpack

(ref

bit

bitstream[],

inputuvm_packer

packer=null);virtual

function

void

record

(uvm_recorder

recorder=null);debugMakecopieschecktransactorrecord

transactions

for

debugger2016/11/27项目经验上E教

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1e没课网专业集成电路Methods

descriptionsMethodsFunctioncloneThe

clone

method

creates

and

returns

an

exact

copy

ofthis

object.

Calls

create

followed

by

copycopyReturns

a

deep

copy

of

this

objectprintDeep-prints

this

object`s

properties

in

a

format

andmanner erned

by

the

given

printer

argumentsprintSame

as

print,

but

returns

a

stringcompareCompare

method

deep

compares

this

data

object

with

theobject

provided

in

the

rhspack/unpackBitwise-concatenate

object`s

properties

into

an

arrayofbits,

bytes

or

intsrecordDeep-records

this

object`s

properties

according

to

anoptional

recorder

policy2016/11/27项目经验上E教

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1e没课网专业集成电路Transaction

methods

usagetransaction

tr0,

tr1,

tr2;bit

bit_stream[];tr0

=

transaction::type_id::create(“tr0”);tr1

=

transaction::type_id::create(“tr1”);tr0.sa

=

10;tr0.print(); //

display

content

of

object

on

stidotr0.copy(tr1);//

copy

content

of

tr1

into

memory

of

tr0//

name

stringis

not

copied$cast

(tr2,

tr1.clone);//

make

tr2

an

exact

duplication

oftr1//

name

string

is

copiedif( pare(tr2))

begin pare

the

contents

of

tr0

against

tr2`uvm_fatal

(“MISMATCH”,

{“\n”,

tr0.sprint(),

tr2.sprint()});end //

sprint()

returns

string

for

loggingtr0.pack(bit_stream); //

pack

content

of

tr0

into

bit_stream

arraytr2.unpack(bit_stream); //

unpack

bit_stream

array

into

tr2

objectName

string2016/11/27项目经验上E教

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1e没课网专业集成电路Transaction

class

methodsHow

create

transactions

manipulation

method?print,

sprint,

clone,

copy,

compare,

record,

pack/unpackUse

macros

to

create

commonly

needed

methods`uvm_object_utils_begin

(transaction_class_name)`uvm_field_*(ARG,

FLAG)`uvm_object_utils_endclass

transaction

extends

uvm_sequence_item;rand

bit

[31:0] sa,

da;rand

bit

[7:0]

payload[$];transaction

tr;`uvm_object_utils_begin

(transaction)`uvm_field_int

(sa,

UVM_ALL_ON

|

UVM_NOCOPY)`uvm_field_int

(da,

UVM_ALL_ON)`uvm_field_queue_int(payload,

UVM_ALL_ON)`uvm_field_object(tr,

UVM_ALL_ON)`uvm_object_utils_endendclass2016/11/27项目经验上E教

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1e没课网专业集成电路uvm_object_utils

Macros`uvm_object_utils

[_begin]

(class_name)Implements

the

followingtypedef

uvm_object_registry

#(class_name,

“class_name”)

type_id;static

const

string

type_name

=

“class_name”;static

function

type_id

get_type();virtual

function

uvm_object_wrapper

get_object_type

();virtual

function

string

get_type_name

();Macro

createsa

proxy

classcalled

type_idclass

uvm_object_registry

#(type

T=uvm_object,

string

Tname=<“unknown”>)

extend

uvm_object_wrapper;typedef

uvm_object_registry

#(T

,

Tname)

this_type;const

static

string

type_name=Tname;local

static

this_type

me

=

get();static

function

this_type

get

();if

(me==null)

beginuvm_factory

f=uvm_factory::get();me

=

new;f.register(me);endreturn

me;endfunctionstatic

function

T

create

(string

name=“”, ponent

parent=null,

string

contxt=“”);static

function

void

set_type_override

(uvm_object_wrapper

override_type,

bit

replace=1);static

function

void

set_inst_override

(uvm_object_wrapper,string

inst_path, ponent

parent=null);virtual

function

string

get_type_name();virtual

function

uvm_object create_object(string

name

=“”);endclassProxy

class

(type_id)

is

a

service

agent

thatcreates

objects

of

the

class

it

representsA

proxy

singleton

object

is

registered

inuvm_factory

at

beginning

of

simulationCreation

of

objects

is

done

viaproxy

class`(type_id)

methods2016/11/27项目经验上E教

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1e没课网专业集成电路`uvm_field_*

Field

macros`uvm_field_*

macros

embed

ARG

properties

in

methodsspecified

by

FLAGScalar

and

array

properties

are

supported//

Any

scalar

numeric

property`uvm_field_int`uvm_field_real`uvm_field_event`uvm_field_object`uvm_field_string(ARG,

FLAG)(ARG,

FLAG)(ARG,

FLAG)(ARG,

FLAG)(ARG,

FLAG)`uvm_field_enum

(T,

ARG,

FLAG)`uvm_field_sarray_*(ARG,

FLAG)`uvm_field_array_*

(ARG,

FLAG)`uvm_field_queue_*(ARG,

FLAG)`uvm_field_aa_*_*

(ARG,

FLAG)//

T

is

enum

data

type//

fixed

size

array:

_type//

dynamic

array:

_type//

queue:

_type//

associative

array:

_type_index2016/11/27项目经验上E教

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1e没课网专业集成电路Methods

specified

by

FLAGFLAG

is

a

collection

of

ON/OFF

bits

associated

with

thebase

class

methods//

A= ,

Y=PHYSICAL,

F=REFERENCE,

S=SHALLOW,

D=DEEP//

K=PACK,

R=RECORD,

P=PRINT, PARE,

C=COPY//

-------------------------- AYFSD

K

R

P

M

Cparameter

UVM_DEFEAUT

=

`b000010101010101;parameter

UVM_ALL_ON

=

`b000000101010101;//

values

are

or

`ed

into

a

32

bit

valueparameterUVM_COPY=

(1<<0);//

copy(…)parameterUVM_NOCOPY=

(1<<1);parameterPARE=

(1<<2);//

compare(…)parameterPARE=

(1<<3);parameterUVM_PRINT=(1<<4);//

print(…)parameterUVM_NOPRINT=

(1<<5);parameterUVM_RECORD=

(1<<6);//

record

(…)parameterUVM_NORECORD=

(1<<7);parameterUVM_PACK=

(1<<8);//

pack

(…)parameterUVM_NOPACK=

(1<<9);//

disable

printing

for

a

hidden

field`uvm_field_int

(hidden_field,UVM_ALL_ON

|

UVM_NOPRINT)2016/11/27项目经验上E教

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1e没课网专业集成电路Print

radix

specified

by

FLAGAdditional

FLAG

can

be

used

to

set

radix

for

print

methodRadix

for

printing

and

recording

can

be

specified

by

OR`ing

one

of

thefollowing

constants

in

the

FLAG

argumentUVM_BINUVM_DECUVM_UNSIGNDEUVM_OCTUVM_HEXUVM_STRINGUVM_TIMEUVM_REAL=>

print/record

field

in

binary

(base-2)=>

print/record

field

in

decimal

(base-10)=>

print/record

field

in

unsigned

decimal

(base-10)=>

print/record

field

in

octal

(base-8)=>

print/record

field

in

hexadecimal

(base-16)=>

print/record

field

in

string

format=>

print/record

field

in

time

format=>

print/record

field

in

floating

number

format//

printing

in

decimal`uvm_field_int

(field,

UVM_ALL_ON

|

UVM_DEC)2016/11/27项目经验上E教

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1e没课网专业集成电路Modify

constraint

in

transactions

by

typeclass

transaction

extends

uvm_sequence_item;rand

bit

[3:0]

sa,

da;rand

bit

[7:0]

payload[];constraint

valid

{payload.size() inside

{[1:10]}};class

transaction_da_3

extends

transaction;constraint

da_3

{da

==

3;}`uvm_object_utils

(transaction_da_3)function

new

(string

name=“transaction_da_super.new(name);endfunctionThe

most

commontransactionmodification

isadding

constraintsclass

test_da_3_type

extends

test_base:` ponent_utils

(test_da_3_type)function

new

(string

name, ponent

parent);super.new(name,

parent);endfunctionvirtual function

void

build_phase

(uvm_phase

phase);super.build_phase(phase);//

set

type_override

(“transaction”,

“transaction_da_3”);set_type_override_by_type

(transaction::get_type(),transaction_da_3::get_type());endfunctionendclassAll

transactioninstances

are

nowtransaction_da_3Preferred

override(compile-time

check)2016/11/27项目经验上E教

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2e没课网专业集成电路Transaction

replacement

resultsin

driverUVM_INFO

@

0:

uvm_test_top.env.i_agent.drv

[Normal]

Itemreg:

(transaction_da_3@95){sa:

‘h7da:

‘h3…}…###

Factory

configuration

(*)Type

overrides:Requested

TypetransactionOverride

Typetransaction_da_3Simulate

with:+UVM_TESTNAME=test_da_3_typeFactory

configuration

is

display

with

a

call

to

:ahb_factory.print()(uvm_factory

ahb_factory=uvm_factory::get())2016/11/27项目经验上E教

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2e没课网专业集成电路Modify

constraint

by

instanceclass

test_da_3_inst

extends

test_base;…

//

utils

and

constructor

not

shownvirtual

function

void

build_phase

(uvm_phase,

phase);super.build_phase(phase);//

set_inst_override

(“env.i_agent*.seqr.*”,

“transaction”,

“pakcet_da_3”);set_inst_override_by_type(“env.i_agent*.seqr.*,

“transaction::get_type(),transaction_da_3::get_type()”);endfunctionendclassUVM_INFO

@

0:

uvm_test_top.env.i_agent.drv

[Normal]

Item

indriverreq:

(test_da_3_inst

@

95)

{sa:

‘h7da:

‘h3}Instance

Overrides:Requested

Type Override

Path Override

Typetransaction

uvm_test_top.env.i_agent*.seqr.*

transaction_da_3Simulate

with:+UVM_TESTNAME=test_da_3_instOnly

transaction

instances

in

matchingsequences

are

now

transaction_da_32016/11/27项目经验上E教

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