老师课件208版-l8-mips数据通路

计算机组成MIPS单周期数据通路航空航天大学计算机学院系统结构计算机科学与技术专业课程航空航天大学计算机学院内容主要取材

CS617的20讲处理器设计数据通路概述组装数据通路控制介绍提纲Great

Idea

#1:

Levels

ofRepresentation/Interpretationlw

$t0,

0($2)lw

$t1,

4($2)sw

$t1,

0($2)sw

$t0,

4($2)Assembly

LanguageProgram

(e.g.

MIPS)MachineLanguageProgram

(MIPS)Higher-Level

LanguageProgram

(e.g.

C)CompilerAssemblertemp

=v[k];v[k]

=

v[k+1];v[k+1]

=

temp;0000

1001

1100

0110

1010

1111

0101

10001010

1111

0101

1000

0000

1001

1100

01101100

0110

1010

1111

0101

1000

0000

10010101

1000

0000

1001

1100

0110

1010

1111MachineInterpretationHardware

ArchitectureDescription(e.g.

block

diagrams)ArchitectureImplementationLogic

Circuit

Description(Circuit

Schematic

Diagrams)We

are

here7/23/2012Summer

2012

--

Lecture

#203systemdatapathcontrolstateregisterscombinationallogicmultiplexer

comparatorcoderegistersregisterlogicswitchingnetworksHardware

Design

HierarchyToday7/23/2012Summer

2012

--

Lecture

#204航空航天大学计算机学院内容主要取材

CS617的20讲处理器设计数据通路概述组装数据通路控制介绍提纲Five

Components

of

a

ComputerComponents

a

computer

needs

to

workControlDatapathMemoryInputOutputProcessorControl(“brain”)Datapath(“brawn”)ComputerMemoryDevices7/23/2012Summer

2012

--

Lecture

#206InputOutputTheProcessorProcessor

(CPU):

Implements

the

instructionsof

the

Instruction

Set

Architecture

(ISA)Datapath:

part

of

the

processor

that

contains

thehardware

necessary

to

perform

operationsrequired

by

the

processor

(“the

brawn”)Control:

part

of

the

processor

(also

in

hardware)which

ls

the

datapath

what

needs

to

be

done(“the

brain”)7/23/2012Summer

2012

--

Lecture

#207Processor

Design

ProcessFive

steps

to

design

a

processor:1.yze

instruction

set

→datapath

requirementsSelect

set

of

datapathcomponents

&

establishclock

methodologyAssemble

datapath

meetingtherequirementsyze

implementation

of

each

instruction

to

determinesetting

of

control

points

that

effects

the

register

transfer4.Assemble

the

control

logicFormula

ogic

EquationsDesign

CircuitsControlDatapathMemoryProcessorInputOutputNow7/23/2012Summer

2012

--

Lecture

#2087/23/2012Summer

2012

--

Lecture

#209The

MIPS-lite

Instruction

SubsetADDU

and

SUBUaddu

rd,rs,rtsubu

rd,rs,rtOR

Immediate:LOAD

andSTORE

Wordlw

rt,rs,imm16sw

rt,rs,imm16BRANCH:–

beq

rs,rt,imm16

6

bitsoprsrtrdshamtfunct0611162126316

bits6

bits5

bits5

bits5

bits5

bitsoprsrtimmediate–

ori

rt,rs,imm16

6

bits0162131

2616

bits5

bits5

bitsoprsrtimmediate0162131

266

bits16

bits5

bits5

bitsoprsrtimmediate01621263116

bits5

bits5

bitsRegister

Transfer

Language

(RTL)All

start

by

fetching

the

instruction:R-format: {op,

rs,

rt,

rd,

shamt,

funct}

MEM[

PC

]I-format: {op,

rs,

rt,

imm16}

MEM[

PC

]RTL

gives

the

meaning

of

the

instructions:Inst Register

TransfersADDU

R[rd]R[rs]+R[rt];

PCPC+4SUBU

R[rd]R[rs]–R[rt];

PCPC+4ORI

R[rt]R[rs]|zero_ext(imm16);

PCPC+4

LOAD

R[rt]MEM[R[rs]+sign_ext(imm16)];

PCPC+4STORE

MEM[R[rs]+sign_ext(imm16)]R[rt];

PCPC+4BEQ if

(

R[rs]

==

R[rt]

)the

PC+4

+

(sign_ext(imm16)

||

00)else

PCPC+47/23/2012Summer

2012

--

Lecture

#20107/23/2012Summer

2012

--

Lecture

#2011Step

1:

Requirements

of

theInstruction

SetMemory

(MEM)Instructions

&

data

(separate:

in

reality

just

caches)Load

from

and

store

toRegisters

(32

32-bit

regs)Read

rs

and

rtWrite

rt

or

rdPCAdd

4

(+

maybe

extended

immediate)Extender

(sign/zero

extend)Add/Sub/OR

unit

for

operation

on

register(s)

orextended

immediateCompare

if

registers

equal?Generic

Datapath

Layout1.

InstructionFetch2.

Decode/ 3.

ExecuteRegister

Read4.

Memory

5.

RegisterWritePCinstructionmemory+4RegisterFilerdrsrtALUDatamemoryimmMUXBreak

up

the

process

of

“executing

an

instruction”Smaller

phases

easier

to

design

and

modify

independentlyProj1

had

3

phases:

Fetch,

Decode,

ExecuteNow

expand

Executeregisterfile~寄存器堆/寄存器文件decode~译码/Step

2:

Components

of

the

Datapath7/23/2012Summer

2012

--

Lecture

#201332AB32Y32MUXMultiplexerALU3232AB32ResultOPALU3232AB32SumCombinational

Elements–

Gates

and

wiresState

Elements

+

ClockBuilding

Blocks:CarryIn

SelectCarryOutAdderAdderMUX设计

1位2选1

MUX表达式：Y=!S&D0+S&D11位4选1

MUX表达式：Y=？Y

=

!S0&!S1&D0

+!S0&

S1&D1

+？S0&!S1&D2

+S0&

S1&D3𝟎1位N选1

MUX表达式𝑵−𝟏𝐘

=

෍

𝑺𝒊&𝑫𝒊Si：S的组合表示Selects

between

one

of

N

inputs

to

connectto

outputlog

N-bit

select

input

–

control

input2Example:2:1MuxSYD0

0D1

1SD1D0YSY00000D000111D1010001111000101011011111Multiplexer

(Mux)01D0D1D2

2D3

3YS[0:1]2MUX设计32位4选1

MUX表达式：?就是32个4选1MUXVerilog表达式assign

Y

=

!S0&!S1&D0

+!S0&

S1&D1

+S0&!S1&D2

+S0&

S1&D3

;M位N选1

MUX表达式？150D0[31:0]D1[31:0]

1D2[31:0]

2D3[31:0]

3Y[31:0]S[0:1]2TIP表达式简写表达方法，即省略了[31:0]前提：D0～D3及Y的位宽一致！ALU

RequirementsMIPS-lite: add,

sub,

OR,

equalityADDUR[rd]=R[rs]+R[rt];...SUBUR[rd]=R[rs]–R[rt];...ORIBEQR[rt]

=

R[rs]

|

zero_ext(Imm16)...if

(

R[rs]

==

R[rt])...Equality

test: Use

subtraction

and

implementoutput

to

indicate

if

result

is

0P&H

also

adds

AND,

Set

Less

Than(1

if

A

<

B,

0otherwise)Can

see

ALU

from

P&H

C.5

(onCD)7/23/2012 Summer

2012

--

Lecture

#20164位加法（无overflow检测）4位减法（采用二进制补码运算方法，即加相反数）VerilogHDL建模4位加法与减法4位加法1234567module

add4(

a,

b,

c

);input

[3:0] a,

b

;output

[3:0] c

;assign

c

=

a

+

b

;endmoduleTIP：Verilog的“+”：最基础的二进制加法，是不区分正负数的！4位减法（无overflow检测）1234567module

sub4(

a,

b,

c

)

;input

[3:0] a,

b

;output

[3:0] c

;assign

c

=

a

+

~b

+

1’b1

;endmoduleTIP：也可以采用assign

c

=

a

–

b

;17VerilogHDL建模4位ALU18ALU的功能：加、减、或加/减：不支持overflowop：控制信号00~加法；01~减法；10~或；11~保留建模方法：利用assign语句实现加法与减法的2选1:::12345`include

“head.v”module

ALU(

a,

b,

c,

op

)

;input

[3:0] a,

b

;input

[1:0] op

;6output[3:0] c

;78assignc

=

(op==`ALU_ADDU)?(a+b)9(op==`ALU_SUBU)?(a+~b+1)10(op==`ALU_OR)?(a|b)11124’b0000

;endmodulehead.v`defineALU_ADDU2’b00`defineALU_SUBU2’b01`defineALU_OR2’b10加减或保留Storage

Element:

RegisterAs

seen

in

Logisim

introN-bit

input

and

output

busesWrite

Enable

inputWrite

Enable:De-asserted

(0):

Data

Out

will

not

changeAsserted

(1):

Data

In

value

placed

onto

Data

Outon

the

rising

edge

of

CLKCLKData

InWrite

EnableNNData

Out7/23/2012Summer

2012

--

Lecture

#2019Storage

Element:

Register

FileRegister

File

consists

of

32

registers:Output

buses

busA

and

busBInput

bus

busWRegister

selectionPlace

data

of

register

RA

(number)

onto

busAPlace

data

of

register

RB

(number)

onto

busBStore

data

on

busW

into

register

RW

(number)

when

WriteEnable

is

1Clock

input

(CLK)CLK

input

is

a

factor

ONLY

during

write

operationDuring

read,

behaves

as

a

combinational

logic

block:

RA

or

RB

valid

→

busA

or

busB

valid

after

“access

time”ClkbusW32busA32busB32Write

Enable

55

5RW

RA

RB32

x

32-bitRegisters7/23/2012Summer

2012

--

Lecture

#2020Register

File设计考虑需要多少个32位寄存器？

读出数据功能：32位31选1

MUX2个读出端口是独立工作无需彼此等待写入数据功能：关键是写使能每个寄存器需要一个写使能DEMUX：分离器/

器DemultiplexerNN位编码产生2

个输出有且仅有1个输出有效ClkbusW32busA32busB32Write

Enable

55

5RW

RA

RB32

x

32-bitRegistersR1R310131013131&&ENENRWbusWWERARB

busAbusBX0

1CLKDEMUX21VerilogHDL建模寄存器221位D寄存器1234567891011module

d_ff(

d,

q,

clk

)

;input d,

clk

;output

q

;reg r

;assign

q

=

r

;

always

@(posedge

clk)r

<=

d;endmodule1位D寄存器：标准的寄存器r：寄存器将r从q输出告诉编译器，以下行为按寄存器建模时钟上升沿时，将输入保存至r23VerilogHDL建模寄存器1位写使能D寄存器1module

d_ff(

d,

we,

q,

clk

)

;2input d,

we

;3output

q

;4input clk

;56reg r

;78assign

q

=

r

;9always

@(

posedge

clk

)10if

(

we

)11r

<=

d;1213endmodule1位写使能D寄存器寄存器建模的完整写法：if

(

we

)r

<=

d;elser

<=

r;Q：为什么可以忽略else？

A：对于缺少的分支，编译器会自动补充“r<=r”。VerilogHDL建模寄存器1位写使能D异步复位寄存器1module

d_ff(

d,

we,

q,

clk,

rst

)

;2input d,

we

;3output

q

;4input clk,

rst

;56reg r

;78assign

q

=

r

;9always

@(

posedge

clk

or

posedge

rst

)10if

(

rst

)11r

<=

1’b0

;12else

if

(

we

)13r

<=

d

;1415endmodule1位写使能D异步复位寄存器TIP：分析方法由于rst在敏感表中，因此rst的有效和clk的有效，均会导致

always语句块执行。这意味着rst对d的作用与clk无关，故这就是异步复位。Q：在设计中如何选择异步复位or同步复位？24VerilogHDL建模寄存器32位写使能寄存器1module

d32(

d,

we,

q,

clk

)

;2input

[31:0]

d

;3input we

;4output

[31:0]

q

;5input clk

;67reg

[31:0]

r

;89assign

q

=

r

;10always

@(

posedge

clk

)11if

(

we)12r

<=

d

;1314endmodule32位写使能寄存器TIP：对于N位寄存器，仅仅改变输入信号、输出信号和寄存器定义的位数即可。25VerilogHDL建模寄存器32位写使能寄存器9101112131415161module

d32(

d,

we,

q,

clk);2input [31:0]

d

;3input we

;4output

[31:0]

q

;5input

clk;67genvari;8generatefor

(

i=0;

i<32;

i=i+1

)begin

:

label_dd_ff

u_dff(d[i],

we,

q[i],

clk)

;endendgenerateendmodule32位写使能寄存器（用generate-for建模。Verilog-2001标准）TIP1）genvar定义循环变量2）必须要有for、begin/end3）begin必须要有26Verilog建模RF0&EN

R1&

EN

R31RWbusWWERARB

busAbusBXCLKwire we[31:1]

;wire

[31:0]

q[31:1]genvar

i

;genvar

j

;generatefor

(

i=1;

i<32;

i=i+1

)begin

:

label_weassign

we[i]

=

(RW==i)

&

WE

;endendgenerategeneratefor

(

j=1;

j<32;

j=j+1

)begin

:

label_d32d32

u_d32(busW,

we[j],

q[j],

clk)

;endendgenerateassign

busA

=

(RA==0)

?

32’b0

:

q[RA]

;assign

busB

=…27采用结构建模方法建模RF其他部分为行为建模用行为建模方法建模RFRF写入语句利用了RW是输入信号（即RW是变值）这一特性Verilog建模RF0&&EN

R1EN

R31RWbusWWERARB

busAbusBXCLKreg [31:0]

rf[31:1]

;always

@(

posedge

clk

)if

(

WE

)rf[RW]

<=

busW

;28assign

busA

=

(RA==0)

?

32’b0

:rf[RA]

;assign

busB

=

…Storage

Element:

Idealized

MemoryMemory(idealized)One

input

bus:

Data

InOne

output

bus:

Data

OutMemory

access:Read:

Write

Enable

=

0,

data

at

Address

is

placed

onData

OutWrite:

Write

Enable

=

1,

Data

In

written

to

AddressClock

input

(CLK)CLK

input

is

a

factor

ONLY

during

write

operationDuring

read,

behaves

as

a

combinational

logic

block:Address

valid

→

Data

Out

valid

after

“access

time”7/23/2012 Summer

2012

--

Lecture

#2029Write

Enable

AddressData

In

DataOut32

32CLK建模要点：

是寄存器阵列时序特点：写入的数据滞后1个cycle输出由寄存器特性决定Verilog建模

器301

module

MEM4KB(

A,DI,

We,DO,clk);2

input

[9:0]A;3

input

[31:0]4

inputDI

;We

;output

[31:0]

DO

;input clk

;78

reg [31:0]

array[1023:0]

;910

assign

DO

=

array[A]

;11always

@(

posedge

clk

)if

(

We)array[A]

<=

DI

;endmoduleTIP：建模类似于RF。实际设计

时，会采用定制的库，而不会用寄存器方式实现

器。对于P8，

器要用FPGA

内置的块

器。航空航天大学计算机学院内容主要取材

CS617的20讲处理器设计数据通路概述组装数据通路控制介绍提纲Datapath

Overview

(1/5)Phase

1:

Instruction

Fetch

(IF)Fetch

32-bit

instruction

from

memoryIncrement

PC

(PC

=

PC

+

4)1.

InstructionFetch2.

Decode/ 3.

ExecuteRegister

Read4.

Memory

5.

RegisterWritePCinstructionmemory+4RegisterFilerdrsrtALUDatamemoryimm7/23/2012Summer

2012

--

Lecture

#2032MUXDatapath

Overview

(2/5)Phase

2:

Instruction

Decode

(ID)Read

the

opcode

and

appropriate

fields

from

theinstructionGather

all

necessary

registers

values

from

Register

File1.

InstructionFetch2.

Decode/

3.

ExecuteRegister

Read4.

Memory

5.

RegisterWritePCinstructionmemory+4RegisterFilerdrsrtALUDatamemoryimm7/23/2012Summer

2012

--

Lecture

#2033MUXDatapath

Overview

(3/5)Phase

3:

Execute

(EX)–

ALU

performs

operations: arithmetic

(+,-,*,/),

shifting,logical

(&,|),

comparisons

(slt,==)1.

InstructionFetch2.

Decode/

3.

ExecuteRegister

Read4.

Memory

5.

RegisterWritePCinstructionmemory+4RegisterFilerdrsrtALUDatamemoryimm–

Also

calculates

addresses

for

loads

and

stores7/23/2012Summer

2012

--

Lecture

#2034MUXDatapath

Overview

(4/5)Phase

4:

Memory

Access

(MEM)Only

load

and

store

instructions

do

anything

during

thisphase;

the

others

remain

idle

or

skip

this

phaseShould

be

fast

due

to

caches1.

InstructionFetch2.

Decode/ 3.

ExecuteRegister

Read4.

Memory

5.

RegisterWritePCinstructionmemory+4RegisterFilerdrsrtALUDatamemoryimm7/23/2012Summer

2012

--

Lecture

#2035MUXDatapath

Overview

(5/5)Phase

5:

Register

Write

(WB

for

“write

back”)Write

the

instruction

result

back

into

the

Register

FileThose

that

don’t

(e.g.

sw,

j,

beq)

remain

idle

or

skip

thisphase1.

InstructionFetch2.

Decode/ 3.

ExecuteRegister

Read4.

Memory

5.

RegisterWritePCinstructionmemory+4RegisterFilerdrsrtALUDatamemoryimm7/23/2012Summer

2012

--

Lecture

#2036MUX7/23/2012Summer

2012

--

Lecture

#2037Why

Five

Stages?Could

we

have

a

different

number

of

stages?Yes,

and

other

architectures

doSo

why

does

MIPS

have

five

if

instructionstend

to

idle

for

at

least

one

stage?The

five

stages

are

the

union

of

all

the

operationsneeded

by

all

the

instructionsThere

is

one

instruction

that

uses

all

five

stages:load

(lw/lb)航空航天大学计算机学院内容主要取材

CS617的20讲处理器设计数据通路概述组装数据通路控制介绍提纲7/23/2012Summer

2012

--

Lecture

#2039Step

3: Assembling

theDatapathAssemble

datapath

to

meet

RTL

requirementsExact

requirements

will

change

based

on

ISAHere

we

will

examine

each

instruction

of

MIPS-liteThe

datapath

is

all

of

the

hardwarecomponents

and

wiring

necessary

to

carry

outall

of

the

different

instructionsMake

sure

all

components

(e.g.

RegFile,

ALU)

haveaccess

to

all

necessary

signals

and

busesControl

will

make

sure

instructions

are

properlyexecuted

(the

decision

making)Datapath

by

InstructionAll

instructions:

Instruction

Fetch

(IF)Fetch

the

Instruction:

mem[PC]Update

the

program

counter:Sequential

Code:PC

PC

+

4Branch

and

Jump:PC

“something

else”Next

AddressLogic32InstructionAddressInstructionMemoryPCCLK7/23/2012Summer

2012

--

Lecture

#2040Datapath

by

InstructionAll

instructions:

Instruction

Decode

(ID)Pull

off

all

relevant

fields

from

instruction

to

makeavailable

to

other

parts

of

datapathMIPS-lite

only

has

R-format

and

I-formatControl

will

sort

out

the

proper

routing

(discussed

later)WiresandSplitters32Instr65555616opcode

rs

rt

rd

shamt

funct

immTIP：原理与一路入户电分成多路室内电相同。以Instr[5:0]为例，分一路为funct，另一路为imm的最低5位。assign

funct

=

Intr[5:0]

;assign

imm

=

Instr[15:0]7/23/2012Summer

2012

--

Lecture

#2041Step

3:

Add

&

SubtractADDU

R[rd]R[rs]+R[rt];Hardware

needed:Instruction

Mem

and

PC

(already

shown)Register

File

(RegFile)

for

read

and

writeALU

for

add/subtractCLKbusW32busA32busB325

5

5RW

RA

RB32

x

32-bitRegisters32ResultALUA32B327/23/2012Summer

2012

--

Lecture

#2042Step

3:

Add

&

SubtractADDU

R[rd]R[rs]+R[rt];Connections:RegFile

and

ALU

InputsConnect

RegFile

and

ALURegWr

(1)

and

ALUctr

(ADD/SUB)

set

by

control

in

ID32ResultbusW32CLKbusA32busB32RW

RA

RB32

x

32-bitRegistersALUctrrd

rs

rtRegWr

5

5

5ALU32AB327/23/2012Summer

2012

--

Lecture

#2043Step

3:

Or

ImmediateORI

R[rt]R[rs]|zero_ext(Imm16);Is

the

hardware

below

sufficient?Zero

extend

imm16?Pass

imm16

to

input

of

ALU?Write

result

to

rt?32ResultCLKbusW32busA32busB32RW

RA

RB32

x

32-bitRegistersALUctrrd

rs

rtRegWr

5

5

5ALU7/23/2012Summer

2012

--

Lecture

#2044Step

3:

Or

ImmediateORI

R[rt]R[rs]|zero_ext(Imm16);Add

new

hardware:Still

support

add/subNew

control

signals:RegDst,

ALUSrc32ALUctrCLK3232busAbusB32RW

RA

RBRegFilers

rtZeroExt3216imm16ALUSrcrd

rt1

0RegWr01ALU5

5

5RegDst2:1

MUXHow

to

implement

this?input [15:0]

imm16

;output

[31:0]

ext32

;assign

ext32

=

{16’b0,

imm16}7/23/2012Summer

2012

--

Lecture

#2045Step

3:

LoadLOAD

R[rt]MEM[R[rs]+sign_ext(Imm16)];Hardware

sufficient?Sign

extend

imm16?Where’s

MEM?32ALUctrCLK3232busAbusB32RW

RA

RBRegFilers

rtZeroExt3216imm16ALUSrcrd

rt1

0RegWr01ALU5

5

5RegDst7/23/2012Summer

2012

--

Lecture

#2046Step

3:

LoadLOAD

R[rt]MEM[R[rs]+sign_ext(Imm16)];New

control

signals:

ExtOp,

MemWr,

MemtoReg32CLKbusW3232busAbusB32RW

RA

RBRegFilers

rtrd

rtRegDstExtender3216imm16ALUSrcExtOpMemtoRegCLKData

In32ALUctrMemWr1

0RegWr01ALU01WrEn

AddrDataMemory5

5

5???Must

nowalso

handlesign

extensionWhatgoeshereduring

astore?设计原则：高内聚，低耦合7/23/2012Summer

2012

--

Lecture

#2047建模要点：二进制补码的扩展方法Verilog建模扩展单元48p,

ext32

)

;?

{16{imm16[15]},

imm16}

:{16’b0,

imm16}

;12module

EXT32(

imm16,

extoinput [15:0]

imm16;3inputextop

;4output[31:0]ext32

;56789assign

ext32

=

extopendmoduleQ：如何改善行6的编码风格以使其可读性更好？A：哪怕extop的选项很少，也应该用宏来定义extop的各个取值。增加可读性是降低代码开发与调试复杂度的重要

。Step

3:

StoreSTORE

MEM[R[rs]+sign_ext(Imm16)]R[rt];Connect

busB

to

Data

In

(no

extra

control

needed!)32CLKbusW3232busAbusB32RW

RA

RBRegFilers

rtrd

rtRegDstExtender3216imm16MemtoReg32Data

InALUctrMemWr1

0RegWr01ALU01WrEn

AddrDataMemory5

5

5CLKALUSrcExtOp7/23/2012Summer

2012

--

Lecture

#2049Step

3:

Branch

If

EqualBEQ

if(R[rs]==R[rt])

the

PC+4

+

(sign_ext(Imm16)

||

00)Need

comparison

output

from

ALU32CLKbusW3232busAbusB32RW

RA

RBRegFilers

rtrd

rtRegDstExtender3216imm16MemtoReg32Data

InALUctrMemWr1

0RegWr01ALU01WrEn

AddrDataMemory5

5

5zero=CLKALUSrcExtOp7/23/2012Summer

2012

--

Lecture

#2050Step

3:

Branch

If

Equalimm16CLK4PC

ExtAdderAdderPCMUX01Instruction32AddrInstructionMemory???

sel

zeroBEQ

if(R[rs]==R[rt])

the

PC+4

+

(sign_ext(Imm16)

||

00)Revisit

“next

address

logic”:How

to

hook

these

up?Signextendand

×4注意：硬件的计算顺序与Instr

Fetch

Unit的计算顺序有本质不同。并行是

性质！Step

3:

Branch

If

EqualBEQ

if(R[rs]==R[rt])

the

PC+4

+(sign_ext(Imm16)

||

00)Revisit

“next

address

logic”:–

_sel

should

be

1

if

branch,

0

otherwise

selMUX01zeroMUXPC+4PC+4

+

branchAddr_sel

zeroMUX000010nextPC

()100111How

does

this

changeif

we

add

bne?7/23/2012Summer

2012

--

Lecture

#2052imm164PC

ExtAdderAdderPCMUX01CLKInstruction32AddrInstructionMemoryInstr

Fetch

UnitBEQ

if(R[rs]==R[rt])

the

PC+4

+

(sign_ext(Imm16)

||

00)Revisit

“next

address

logic”:

sel

zeroStep

3:

Branch

If

Equal7/23/2012Summer

2012

--

Lecture

#2053航空航天大学计算机学院内容主要取材

CS617的20讲处理器设计数据通路概述组装数据通路控制介绍提纲Processor

Design

ProcessFive

steps

to

design

a

processor:1.yze

instruction

set

→datapath

requirementsSelect

set

of

datapathcomponents

&

establishclock

methodologyAssemble

datapath

meetingthe

requirements4.yze

implementation

of

each

instruction

to

determinesetting

of

control

points

that

effects

the

register

transferAssemble

the

control

logicFormula

ogic

EquationsDesign

CircuitsControlDatapathMemoryProcessorInputOutputNow7/23/2012Summer

2012

--

Lecture

#20557/23/2012Summer

2012

--

Lecture

#2056ControlNeed

to

make

sure

that

correct

parts

of

thedatapath

are

being

used

for

each

instructionHave

seen

control

signals

in

datapath

used

toselect

inputs

and

operationsFor

now,

focus

on

what

value

each

control

signalshould

be

for

each

instruction

in

the

ISANext

lecture,

we

will

see

how

to

implement

theproper

combinational

logic

to

implement

thecontrolMIPS-lite

Datapath

Control

SignalsExtOp:ALUsrc:ALUctr:_sel:0

→

“zero”;

1

→

“sign”0

→

busB;

1

→

imm16“ADD”,

“SUB”,

“OR”0

→

+4;

1

→

branchMemWr:MemtoReg:RegDst:RegWr:1

→

write

memory0

→

ALU;

1

→

Mem0

→

“rt”;

1

→

“rd”1

→

write

registerALUctrCLKbusW3232busAbusB32rs

rtrd

rtRegDstExtender16imm1632ALUSrcExtOpMemtoRegCLK32Data

InMemWr321

0RegWrRW

RA

RBRegFile01ALU01WrEn

AddrDataMemory5

5

5zero=

selInstrFetchUnitCLK7/23/2012Summer

2012

--

Lecture

#2057Desired

Datapath

For

adduR[rd]R[rs]+R[rt];32CLKbusW32busAbusB32Extender3216imm16CLK32Data

InRW

RA

RBRegFile01ALU01WrEn

AddrDataMemoryrs

rt5

5

5zero32=Instruction

<31:0><21:25><16:20><11:15><0:15>InstrFetchUnitCLK

sel=+4RegDst=1rd

rt1

0RegWr=1rs

rt

rd

imm16ALUctr=ADDMemtoReg=0MemWr=0ALUSrc=0ExtOp=X7/23/2012Summer

2012

--

Lecture

#2058Desired

Datapath

For

oriR[rt]R[rs]|ZeroExt(imm16);32CLKbusW32busAbusbBusB32rs

rtExtender16imm16CLK32Data

InRW

RA

RBRegFile01ALU01WrEn

AddrDataMemory5

5

5zero32=Instruction

<31::0><21:25><16:20><11:15><0:15>imm16InstrFetchUnitCLK

sel=+4RegDst=0rd