集成电路设计-08-子系统设计

集成电路设计第八章

子系统设计

1EIS-WuhanUniversityOutline加法器移位器存储器ROMRAM2EIS-WuhanUniversityAGenericDigitalProcessorMEMORYDATAPATHCONTROLINPUT-OUTPUT9-1运算电路（ArithmeticCircuits）概述3EIS-WuhanUniversityBuildingBlocksforDigitalArchitecturesArithmeticunit-

Bit-sliceddatapath(adder,multiplier,shifter,comparator,etc.)Memory-RAM,ROM,Buffers,ShiftregistersControl-Finitestatemachine(PLA,randomlogic.)-CountersInterconnect-Switches-Arbiters-Bus4EIS-WuhanUniversityAnIntelMicroprocessorItaniumhas6integerexecutionunitslikethis5EIS-WuhanUniversity位片式Bit-SlicedDesignBit3Bit2Bit1Bit0RegisterAdderShifterMultiplexerControlData-InData-OutTileidenticalprocessingelements6EIS-WuhanUniversityBit-SlicedDatapath7EIS-WuhanUniversity9-2AddersFull-Adder逐位进位（Ripple-Carry）加法器镜像加法器TransmissionGateFullAdder进位旁路加法器超前进位LookAhead加法器8EIS-WuhanUniversityThe1-bitBinaryFull-AdderHowcanwemodifyiteasilytobuildanadder?Howcanwemakeitbetter(faster,lowerpower,smaller)?generategeneratepropagatepropagatepropagatepropagatekillkillcarrystatus1111101011011011000101110100101010000000SCoutCinBA1-bitFullAdder(FA)ABSCinCout9EIS-WuhanUniversityTheBinaryAdderG=A&BP=ABK=!A&!BS=AB

Cin=P

Cin

Cout=A&B|A&Cin|B&Cin =G|P&Cin

10EIS-WuhanUniversityExpressSumandCarryasafunctionofP,G,DDefine3newvariablewhichONLYdependonA,BGenerate(G)=ABPropagate(P)=AÅBDelete=A

B11EIS-WuhanUniversity逐位进位（Ripple-Carry）加法器WorstcasedelaylinearwiththenumberofbitsGoal:Makethefastestpossiblecarrypathcircuittd=O(N)tadder=(N-1)tcarry+tsumFAFAFAFAA0B0S0A1B1S1A2B2S2A3B3S3Ci,0Co,0(=Ci,1)Co,1Co,2Co,312EIS-WuhanUniversityComplimentaryStaticCMOSFullAdder28Transistors13EIS-WuhanUniversity反相特性InversionPropertyABSCoCiFAABSCoCiFA输入反相，输出也反相。14EIS-WuhanUniversityMinimizeCriticalPathbyReducingInvertingStagesA3FAFAFAEvencellOddcellFAA0B0S0A1B1S1A2B2S2B3S3Ci,0Co,0Co,1Co,3Co,2在进位链中减少反相器数目。15EIS-WuhanUniversity镜像加法器（TheMirrorAdder）VDDCiABBABAABKillGenerate"1"-Propagate"0"-PropagateVDDCiABCiCiBACiABBAVDDSCo24transistors去掉了反相器；PUN与PDN不对称，延迟时间减少16EIS-WuhanUniversityMirrorAdderStickDiagram17EIS-WuhanUniversityTransmissionGateFullAdderABPCiVDDAAAVDDCiAPABVDDVDDCiCiCoSCiPPPPPSumGenerationCarryGenerationSetup18EIS-WuhanUniversityManchesterCarryChainGenerate(G)=ABPropagate(P)=AÅBDelete=A

B动态实现19EIS-WuhanUniversityManchesterCarryChain20EIS-WuhanUniversityManchesterCarryChainStickDiagram21EIS-WuhanUniversity进位旁路加法器Carry-BypassAdderFAFAFAFAP0G1P1G1P2G2P3G3Co,3Co,2Co,1Co,0Ci,0FAFAFAFAP0G1P1G1P2G2P3G3Co,2Co,1Co,0Ci,0Co,3MultiplexerBP=PoP1P2P3Idea:If(P0andP1andP2andP3=1)thenCo3=Ci0,else“kill”or“generate”.22EIS-WuhanUniversityCinCout可用于16、32、64bit的sum运算。代价：10-20%23EIS-WuhanUniversitytadder=tsetup+Mtcarry+(N/M-1)tbypass+(M-1)tcarry+tsumCarrypropagationSetupBit0–3SumMbitstsetuptsumCarrypropagationSetupBit4–7SumtbypassCarrypropagationSetupBit8–11SumCarrypropagationSetupBit12–15Sum形成进位产生、传播需要的时间通过旁路开关的传播延迟通过求和的延迟通过一位的传播延迟第一级最后一级关键路径24EIS-WuhanUniversityCarryRippleversusCarryBypass25EIS-WuhanUniversity超前进位LookAhead加法器ExpandingLookaheadequations:Alltheway:26EIS-WuhanUniversityAN-1,BN-1A1,B1P1S1••••••SN-1PN-1Ci,N-1S0P0Ci,0Ci,1A0,B027EIS-WuhanUniversityLook-Ahead:TopologyCo,3Ci,0VDDP0P1P2P3G0G1G2G328EIS-WuhanUniversityLogarithmicLook-AheadAdderA7FA6A5A4A3A2A1A0A0A1A2A3A4A5A6A7Ftp~log2(N)tp~N29EIS-WuhanUniversityCarryLookaheadTreesCancontinuebuildingthetreehierarchically.30EIS-WuhanUniversity9-3移位器Shifters

——TheBinaryShifterAiAi-1BiBi-1RightLeftnopBit-Slicei...31EIS-WuhanUniversity桶形移位器TheBarrelShifterAreaDominatedbyWiringSh3Sh2Sh1Sh0Sh3Sh2Sh1A3A2A1A0B3B2B1B0:ControlWire:DataWire32EIS-WuhanUniversity对数移位器LogarithmicShifter

——分级实现Sh1Sh1Sh2Sh2Sh4Sh4A3A2A1A0B1B0B2B333EIS-WuhanUniversity9-4存储器MemoriesMemoryClassificationMemoryArchitecturesTheMemoryCoreROMEPROMEEPROMFLASHRAMSRAMDRAM34EIS-WuhanUniversitySemiconductorMemoryClassificationRead-WriteMemoryNon-VolatileRead-Write

MemoryRead-OnlyMemoryEPROME2PROMFLASHRandomAccessNon-RandomAccessSRAMDRAMMask-ProgrammedProgrammable(PROM)FIFOShiftRegisterCAM（contents）LIFO35EIS-WuhanUniversityMemoryTiming:DefinitionsReadReadCycleReadAccessReadAccessWriteWriteCycleDataWriteSetupDataValidWriteHold36EIS-WuhanUniversityMemoryArchitecture:DecodersWord0Word1Word2WordN-2WordN-1StoragecellMbitsMbitsNwordsS0S1S2SN-2A0A1AK-1K=log2NSN-1Word0Word1Word2WordN-2WordN-1StoragecellS0Input-Output(Mbits)直接实现NxMmemoryNwords==NselectsignalsK=log2NDecoderreducesthenumberofselectsignalsInput-Output(Mbits)Decoder译码器37EIS-WuhanUniversityArray-StructuredMemoryArchitectureA0RowDecoderA1Aj-1SenseAmplifiersbitlinewordlinestorage(RAM)cellRowAddressColumnAddressAjAj+1Ak-1Read/WriteCircuitsColumnDecoder2k-jm2jInput/Output(mbits)amplifiesbitlineswingselectsappropriatewordfrommemoryrow38EIS-WuhanUniversityHierarchicalMemoryArchitectureAdvantages:1.Shorterwireswithinblocks2.Blockaddressactivatesonly1block=>powersavings39EIS-WuhanUniversityRead-OnlyMemoryCellsWordLineBitLineWLBL1WLBLWLBLWLBL0VDDWLBLGNDDiodeROMMOSROM1MOSROM240EIS-WuhanUniversityMOSORROMWL[0]VDDBL[0]WL[1]WL[2]WL[3]VbiasBL[1]Pull-downloadsBL[2]BL[3]VDD41EIS-WuhanUniversityMOSNORROMWL[0]GNDBL[0]WL[1]WL[2]WL[3]VDDBL[1]Pull-updevicesBL[2]BL[3]GND42EIS-WuhanUniversityMOSNANDROMAllwordlineshighbydefaultwithexceptionofselectedrowWL[0]WL[1]WL[2]WL[3]VDDPull-updevicesBL[3]BL[2]BL[1]BL[0]无电源线串联结构—减少布线43EIS-WuhanUniversityEquivalentTransientModelforMOSNORROMWordlineparasiticsWirecapacitanceandgatecapacitanceWireresistance(polysilicon)BitlineparasiticsResistancenotdominant(metal)DrainandGate-DraincapacitanceVDDCbitrwordcwordWLBL44EIS-WuhanUniversityDecreasingWordLineDelayMetalbypassPolysiliconwordlineKcellsPolysiliconwordlineWLDriver(b)Usingametalbypass(a)DrivingthewordlinefrombothsidesMetalwordlineWL45EIS-WuhanUniversityPrechargedMOSNORROMWL[0]GNDBL[0]WL[1]WL[2]WL[3]VDDBL[1]PrechargedevicesBL[2]BL[3]GNDpref解决：静态功耗问题；有比逻辑问题。46EIS-WuhanUniversityNon-VolatileMemories

浮栅晶体管Floating-gatetransistor(FAMOS)FloatinggateSourceSubstrateGateDrainn+n+_ptoxtoxDevicecross-sectionSchematicsymbolGSD浮栅使栅氧层加大；

使阈值电压提高。A—Avalancheinjection47EIS-WuhanUniversityFloating-GateTransistorProgramming0V-5V0VDSRemovingprogrammingvoltageleaveschargetrapped5V-2.5V5VDSProgrammingresultsin

higherVT.20V10V5V20VDS雪崩注入Avalancheinjection绝缘体48EIS-WuhanUniversityA“Programmable-Threshold”Transistor浮栅上存储了电荷后，使开启电压提高到7V左右，

5V栅源电压下，晶体管不工作。49EIS-WuhanUniversity电擦除可编程只读存储器

——EEPROMCellWLBLVDD2transistorcell集成度低被编程后，浮栅MOS管具有较高的开启电压，施加正常的VDD将处于关闭状态；未被编程的浮栅MOS等同于正常MOS，处于导通状态。50EIS-WuhanUniversityFlashEEPROMControlgate擦除erasurep-substrateFloatinggate薄隧道氧化层Thintunnelingoxiden+sourcen+drain编程programming编程：栅、漏=高电压（12V），源接地；擦除：栅接地，源=12V。（1984）51EIS-WuhanUniversityNORFlashMemory―Erase52EIS-WuhanUniversityNORFlashMemory―Write53EIS-WuhanUniversityNORFlashMemory―Read上拉54EIS-WuhanUniversityNANDFlashMemoryUnitCellWordline(poly)Sourceline(Diff.Layer)55EIS-WuhanUniversityNANDFlashMemoryWordlinesSelecttransistorBitlinecontactSourcelinecontactActiveareaSTICourtesyToshiba56EIS-WuhanUniversityCharacteristicsofNVM57EIS-WuhanUniversityRead-WriteMemories(RAM)STATIC(SRAM)DatastoredaslongassupplyisappliedLarge(6transistors/cell)FastDifferential

DYNAMIC(DRAM)PeriodicrefreshrequiredSmall(1-3transistors/cell)SlowerSingleEnded58EIS-WuhanUniversity6-transistorCMOSSRAMCellWLBLVDDM5M6M4M1M2M3BLQQ59EIS-WuhanUniversityCMOSSRAMAnalysis(Read)WLBLVDDM5M6M4M1VDDVDDVDDBLQ=1Q=0CbitCbit预充电至VDD60EIS-WuhanUniversityCMOSSRAMAnalysis(Read)000.811.20.5Voltagerise[V]11.21.52CellRatio(CR)2.53VoltageRise(V)Q选择合适的CR，防止影响存储的信息。61EIS-WuhanUniversityCMOSSRAMAnalysis(Write)BL=1BL=0Q=0Q=1M1M4M5M6VDDVDDWLQ：1062EIS-WuhanUniversityCMOSSRAMAnalysis(Write)PR=(W4/L4)/(W6/L6)63EIS-WuhanUniversity6T-SRAM—LayoutVDDGNDQQWLBLBLM1M3M4M2M5M664EIS-WuhanUniversityResistance-loadSRAMCellStaticpowerdissipation--WantRLlargeBitlinesprechargedtoVDDtoaddresstpproblemM3RLRLVDDWLQQM1M2M4BLBL65EIS-WuhanUniversity3-TransistorDRAMCellNoconstraintsondeviceratiosReadsarenon-destructiveValuestoredatnodeXwhenwritinga“1”=VWWL-VTnWWLBL1M1XM3M2CSBL2RWLVDDVDD-VTΔVVDD-VTBL2BL1XRWLWWLBL2预充电至VDD或VDD-Vt66EIS-WuhanUniversity1-TransistorDRAMCellWrite:CSischargedordischargedbyassertin