EDA设计参考程序完整版,合计31题资料

1、设计一个带计数使能、异步复位、带进位输出的减 1三位二进制计数器，结果由共阴极七段数码管显示。libraryieee;entitycounterisport(clk,en,clr:instd_logic;ledout:outstd_logic_vector(6downto0);co:outstd_logic);endcounter;architectureaofcounterissignalcnt:std_logic_vector(2downto0);signalhex:std_logic_vector(2downto0);beginprocess(clk)beginifclr='1'thencnt<=(others=>'0');elsif(clk'eventandclk='1')thenifen='1'thenifcnt="000"thencnt<="111";co<='1';elsecnt<=cnt-'1';co<='0';endif;endif;endif;endprocess;hex<=cnt(2downto0);withhexselectledout<="0000111"when"111","1111101"when"110","1101101"when"101","1100110"when"100","1001111"when"011","1011011"when"010","0000110"when"001","0111111"whenothers;enda;2、设计一个带计数使能、同步复位、带进位输出的增 1十进制计数器，计数结果由共阴极七段数码管显示。LIBRARYIEEE;ENTITYcounter3ISPORT(clk,clr,en :INSTD_LOGIC;co :OUT STD_LOGIC;ledout :OUT STD_LOGIC_VECTOR(6downto0));ENDcounter3;ARCHITECTUREaOFcounter3ISSIGNALcnt :STD_LOGIC_VECTOR(3downto0);SIGNALled :STD_LOGIC_VECTOR(6downto0);BEGINcnt<=(OTHERS=>'0');ELSIFEN='1'THENIFcnt="1001"THENcnt<="0000";co<='1';cnt<=cnt+'1';co<='0';ENDIF;ENDIF;ENDIF;ENDPROCESS;ledout<=NOTled;WITHcntSELECTled<="1111001"WHEN"0001",--1"0100100"WHEN"0010",--2"0110000"WHEN"0011",--3"0011001"WHEN"0100",--4"0010010"WHEN"0101",--5"0000010"WHEN"0110",--6"1111000"WHEN"0111",--7"0000000"WHEN"1000",--8"0010000"WHEN"1001",--9"1000000"WHENothers;--0ENDa;3、设计一个带计数使能、异步复位、同步装载的可逆三位二进制计数器，计数结果由共阴极七段数码管显示。libraryieee;entitycounterisport(clk,clr,en,stld,upon:instd_logic;din:instd_logic_vector(2downto0);q:outstd_logic_vector(6downto0));endcounter;architectureaofcounterissignalcnt:std_logic_vector(2downto0);signaly:std_logic_vector(6downto0);beginprocess(clk)beginifclr='1'thencnt<="000";elsifclk'eventandclk='1'thenifstld='1'thencnt<=din;elsifen='1'thenifupon='0'thencnt<=cnt-'1';elsecnt<=cnt+'1';endif;endif;endif;endprocess;q<=NOTy;WITHcntSELECTy<="1111001"WHEN"001",--1"0100100"WHEN"010",--2"0110000"WHEN"011",--3"0011001"WHEN"100",--4"0010010"WHEN"101",--5"0000010"WHEN"110",--6"1111000"WHEN"111",--7"1000000"WHENothers;--0enda;4、设计一个带计数使能、同步复位、异步装载、可逆计数的通用计数器。计数结果由共阴极七段数码管显示。entityasdasdsadxvzzxisGeneric(count_value:INTEGER:=9);Port(clk:in STD_LOGIC;clr:in STD_LOGIC;en:in STD_LOGIC;load:in STD_LOGIC;dir:in STD_LOGIC;data_in:inINTEGERRANGE0TOcount_value;ledout:outSTD_LOGIC_VECTOR(6downto0));endasdasdsadxvzzx;architectureBehavioralofasdasdsadxvzzxisSIGNALcnt:INTEGERRANGE0TOcount_value;SIGNALled:STD_LOGIC_VECTOR(6DOWNTO0);beginPROCESS(load,clk)beginIFload='1'THENcnt<=data_in;ELSIF(clk'eventandclk='1')THENIFclr='1'thencnt<=0;elsifen='1'thenifdir='1'thenifcnt=count_valuethencnt<=0;elsecnt<=cnt+1;endif;elseifcnt=0thencnt<=count_value;elsecnt<=cnt-1;endif;endif;endif;endif;endprocess;ledout<=NOTled;withcntselectled<="1111001"WHEN1,--1"0100100"WHEN2,--2"0110000"WHEN3,--3"0011001"WHEN4,--4"0010010"WHEN5,--5"0000010"WHEN6,--6"1111000"WHEN7,--7"0000000"WHEN8,--8"0010000"WHEN9,--9"1000000"WHEN0,--0"1111111"WHENothers;endBehavioral;5、设计一个具有16分频、8分频、4分频和2分频功能的分频器libraryieee;entityclkdivisport(clk:instd_logic;clk_div2:outstd_logic;clk_div4:outstd_logic;clk_div8:outstd_logic;clk_div16:outstd_logic);endclkdiv;architecturertlofclkdivissignalcount:std_logic_vector(3downto0);beginprocess(clk)beginif(clk'eventandclk='1')thenif(count="1111")thencount<=(others=>'0');elsecount<=count+1;endif;endif;endprocess;clk_div2<=count(0);clk_div4<=count(1);clk_div8<=count(2);clk_div16<=count(3);endrtl;法二LIBRARYIEEE;ENTITYdiv4ISPORT(clk:INSTD_LOGIC;din:INSTD_LOGIC_VECTOR(3DOWNTO0);reset:INSTD_LOGIC;fout:OUTstd_LOGIC);ENDdiv4;ARCHITECTUREaOFdiv4ISbeginprocess(clk)variablecnt:std_logic_vector(3downto0):="0000";beginifreset='1'thenfout<='0';elsif(clk'eventandclk='1')thenifcnt="1111"thencnt:="0000";elsecnt:=cnt+'1';endif;ifdin="0000"thenfout<=cnt(3);elsifdin="1000"thenfout<=cnt(2);elsifdin="1100"thenfout<=cnt(1);elsifdin<="1110"thenfout<=cnt(0);elsefout<='1';endif;endif;endprocess;enda;6、设计一个正负脉宽相等的通用分频器LIBRARYIEEE;ENTITYcounterISGENERIC(count_value:INTEGER:=15);PORT(clk,clr,en:INSTD_LOGIC;count:OUTSTD_LOGIC);ENDcounter;ARCHITECTUREaOFcounterISSIGNALcnt:INTEGERRANGE0TOcount_value;SIGNALco:STD_LOGIC;SIGNALcount1:STD_LOGIC;BEGINPROCESS(clk,clr)BEGINIFclr='1'THENcnt<=0;ELSIF(clk'EVENTANDclk='1')THENIFen='1'THENIFcnt=count_valueTHENcnt<=0;co<='1';ELSEcnt<=cnt+1;co<='0';ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(co)BEGINIF(co'EVENTANDco='1')THENcount1<=NOTcount1;ENDIF;count<=count1;ENDPROCESS;ENDa;法二：LIBRARYIEEE;ENTITYdivISGENERIC(num:INTEGER:=2);PORT(clk:INSTD_LOGIC;reset:INSTD_LOGIC;co:OUTSTD_LOGIC);ENDdiv;ARCHITECTURErtlOFdivISBEGINPROCESS(clk)VARIABLEcnt:STD_LOGIC_VECTOR(numdownto0):=(others=>'0');BEGINIFreset='1'thenco<='0';ELSIF(clk'eventandclk='1')THENcnt:=cnt+'1';ENDIF;co<=cnt(num);ENDPROCESS;ENDrtl;7、设计一个正负脉宽可控的 4分频的分频器LIBRARYIEEE;ENTITYdivISPORT(clk,rst:INSTD_LOGIC;din:INSTD_LOGIC_VECTOR(1DOWNTO0);COUNT:OUTSTD_LOGIC);ENDdiv;ARCHITECTURErtlOFdivISSIGNALco:STD_LOGIC;BEGINPROCESS(clk)VARIABLEcnt:STD_LOGIC_VECTOR(1DOWNTO0);BEGINifrst='1'thenco<='0';cnt:="00";elsif(clk'eventandclk='1')thenif(cnt="11")thencnt:="00";co<=notco;elsif(cnt=din)thenco<=notco;cnt:=cnt+'1';elsecnt:=cnt+'1';endif;endif;endprocess;count<=co;endrtl;8根据需要设计一个分频器：可以控制实现四种分频形式：第一种： 5分频、第二种： 8分频、第三种：15分频、第四种： 16分频(其中8分频和16分频为正负脉宽相等的分频器 )libraryieee;entityfenpinisport(clk:instd_logic;en:instd_logic_vector(1downto0);cout:outstd_logic);endfenpin;architecturedgnfenpinoffenpinissignalhex:std_logic_vector(3downto0);beginprocess(clk)variablecnt:std_logic_vector(3downto0);beginif(clk'eventANDclk='1')thenif(en="00")thenif(cnt>="0111")thencnt:="0000";

--8

分频elsecnt:=cnt+'1';endif;cout<=cnt(2);elsif(en="01")thenif(cnt>="0100")thencnt:="0000";cout<='1';

--5分频elsecnt:=cnt+'1';cout<='0';endif;elsif(en="10")thenif(cnt>="1110")thencnt:="0000";cout<='1';elsecnt:=cnt+'1';cout<='0';--15 分频endif;elseif(cnt>="1111")thencnt:="0000";--16分频elsecnt:=cnt+'1';endif;cout<=cnt(3);endif;endif;endprocess;enddgnfenpin;9、设计一个M序列发生器， M序列为“11110101”LIBRARYIEEE;entityseqisPort(clk:in STD_LOGIC;fout:out STD_LOGIC);endseq;architectureBehavioralofseqissignalcnt:std_logic_vector(2downto0);beginprocess(clk)beginif(clk'eventandclk='1')thenifcnt="111"thencnt<="000";elsecnt<=cnt+'1';endif;endif;endprocess;withcntselectfout<='1'when"000",'1'when"001",'1'when"010",'1'when"011",'0'when"100",'1'when"101",'0'when"110",'1'whenothers;endBehavioral;10、 设计一个彩灯控制器，彩灯共有 6个，每次顺序点亮相邻的 2个彩灯，如此循环执行，循环的方向可以控制LIBRARYIEEE;entitycaidengisPort(clk:in STD_LOGIC;rl:in STD_LOGIC;ledout:out STD_LOGIC_VECTOR(5downto0));endcaideng;architectureBehavioralofcaidengissignalled:STD_LOGIC_VECTOR(5downto0):=(others=>'0');signalk:STD_LOGIC:='0';beginprocess(clk)beginif(clk'eventandclk='1')thenif(k='0')thenled<=(0=>'0',1=>'0',others=>'1');k<='1';elsif(rl='1')thenled<=led(4downto0)&led(5);elsif(rl='0')thenled<=led(0)&led(5downto1);endif;endif;ledout<=led;endprocess;endBehavioral;11、设计一个具有左移、右移控制，同步并行装载和串行装载的LIBRARYIEEE;ENTITYshifter1ISPORT(clk,clr,ser,dir,stld:INSTD_LOGIC;din:INSTD_LOGIC_VECTOR(0TO3);qh:OUTSTD_LOGIC_VECTOR(0TO3));ENDshifter1;ARCHITECTURErt1OFshifter1ISSIGNALreg:STD_LOGIC_VECTOR(0TO3):=(others=>'0');beginprocess(clk,clr)beginifclr='1'then

4位串行移位寄存器reg<=(others=>'0');elsifclk'eventandclk='1'thenifstld='0'thenreg<=din;elseif(dir='0')thenreg<=reg(1to3)&ser;qh<=reg(0);elsereg<=ser®(0to2);qh<=reg(3);endif;endif;endif;endprocess;endrt1;12、设计一个4人表决电路，参加表决者为4人，同意为1，不同意为0，同意者过半则表决通过，绿指示灯亮，表决不通过则红指示灯亮。同意与不同意人数相等时，两灯同时亮起。数码管显示赞成人数。libraryieee;entityselectorisport(a:instd_logic_vector(3downto0);r,g:outstd_logic;ledout:outstd_logic_vector(6downto0));endselector;architecturert1ofselectorissignalled:std_logic_vector(6downto0);signalcount:std_logic_vector(2downto0);beginprocess(a)variablecnt:std_logic_vector(2downto0);begincnt:="000";foriin0to3loopifa(i)='1'thencnt:=cnt+1;endif;endloop;if(cnt>="100"orcnt<="011")theng<='0';r<='1';elsif(cnt>="010")theng<='0';r<='0';elsif(cnt>="000"orcnt<="001")theng<='1';r<='0';endif;count<=cnt;endprocess;ledout<=notled;withcountselectled<="1111001"when"0001",--1"0100100"when"0010",--2"0110000"when"0011",--3"0011001"when"0100",--4"1000000"whenothers;--0endrt1;13、 设计一个同步复位，异步并行装载的 4位串行左移移位寄存器方法一：LIBRARYIEEE;ENTITYshifterISPORT(clk,clr,ser,stld:INSTD_LOGIC;din:INSTD_LOGIC_VECTOR(0TO3);qh:OUTSTD_LOGIC);ENDshifter;ARCHITECTURErt1OFshifterISSIGNALreg:STD_LOGIC_VECTOR(0TO3);beginprocess(clk,clr)beginifclr='1'thenreg<=(others=>'0');elsifclk'eventandclk='1'thenifstld='0'thenreg<=din;elsereg<=reg(1to3)&ser;endif;endif;endprocess;qh<=reg(0);endrt1;方法二：a,b,c,d:4位并行数据输入端ser--串行数据输入端 clk--时钟信号输入端 clkin--时钟信号禁示端stld--移位装载控制端 clr--清零复位端 q--串行数据输出端LIBRARYIEEE;ENTITYshifterISPORT(clr,ser,clkin,clk,stld,a,b,c,d:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDshifter;ARCHITECTURErt1OFshifterISSIGNALdin:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALreg:STD_LOGIC_VECTOR(3DOWNTO0);BEGINdin<=a&b&c&d;PROCESS(clk,clr)BEGINIFstld='0'THEN --（异步并行装载）reg<=din;ELSIFclk'eventandclk='1'THENIFclkin='0'THENIFclr='1'THEN --（同步复位）reg<=(others=>'0');ELSEreg<=ser®(3downto1); --（串行左移）ENDIF;ENDIF;ENDIF;ENDPROCESS;q<=reg(0);ENDrt1;14、 有16个开关，编号为 0到15，编号0的优先级最高。当某一个拨码开关为 1时由共阴极七段数码管显示其编号LIBRARYIEEE;ENTITYbhxsISPORT(INPUT:INSTD_LOGIC_VECTOR(15DOWNTO0);LEDOUT:outSTD_LOGIC_VECTOR(6DOWNTO0));ENDbhxs;ARCHITECTURERT1OFbhxsISSIGNALLED:STD_LOGIC_VECTOR(6DOWNTO0);BEGINprocess(INPUT)beginLEDOUT<=LED;IF(INPUT(0)='1')thenLED<="1000000";ELSIF(INPUT(1)='1')thenLED<="1111001";ELSIF(INPUT(2)='1')thenLED<="0100100";ELSIF(INPUT(3)='1')thenLED<="0110000";ELSIF(INPUT(4)='1')thenLED<="0011001";ELSIF(INPUT(5)='1')thenLED<="0010010";ELSIF(INPUT(6)='1')thenLED<="0000010";ELSIF(INPUT(7)='1')thenLED<="1111000";ELSIF(INPUT(8)='1')thenLED<="0000000";ELSIF(INPUT(9)='1')thenLED<="0010000";ELSIF(INPUT(10)='1')thenLED<="0001000";ELSIF(INPUT(11)='1')thenLED<="0000011";ELSIF(INPUT(12)='1')thenLED<="1000110";ELSIF(INPUT(13)='1')thenLED<="0100001";ELSIF(INPUT(14)='1')thenLED<="0000110";ELSIF(INPUT(15)='1')thenLED<="0001110";ENDIF;ENDPROCESS;ENDRT1;15、设计一个全自动洗衣机水位控制器。要求：当水位超过某一上限值时，停止加水，启动洗衣机；当水位低于某一下限值时，加水，停止洗衣机；否则启动洗衣机，停止加水。LIBRARYIEEE;ENTITYxiyijiISPORT(clk,water_high,water_low:INSTD_LOGIC;jiashui,qitong:OUTSTD_LOGIC);ENDxiyiji;ARCHITECTUREstyleOFxiyijiISTYPEstateIS(just_right,too_high,too_low);SIGNALnow_state,next_state:state;BEGINPROCESS(now_state,water_high,water_low)BEGINCASEnow_stateISWHENjust_right=>jiashui<='0';qitong<='1';IFwater_low='1'THENnext_state<=too_low;ELSIFwater_high='1'THENnext_state<=too_high;ELSE next_state<=just_right;ENDIF;WHENtoo_low=>jiashui<='1';qitong<='0';IFwater_low='1'THENnext_state<=too_low;ELSIFwater_high='1'THENnext_state<=too_high;ELSE next_state<=just_right;ENDIF;WHENtoo_high=>jiashui<='0';qitong<='1';IFwater_low='1'THENnext_state<=too_low;ELSIFwater_high='1'THENnext_state<=too_high;ELSE next_state<=just_right;ENDIF;ENDCASE;ENDPROCESS;PROCESS(clk)BEGINIF(clk'eventANDclk='1')THENnow_state<=next_state;ENDIF;ENDPROCESS;ENDstyle;方法二；LIBRARYIEEE;entitywasherisPort(clk:in STD_LOGIC;tmp_low:in STD_LOGIC;wash:out STD_LOGIC;water:out STD_LOGIC);endwasher;architectureBehavioralofwasheristypestateis(work,unwork);signalnow_state,next_state:state;beginprocess(now_state,tmp_low)begincasenow_stateiswhenwork=>wash<='1';water<='0';if(tmp_low='1')thennext_state<=unwork;elsenext_state<=work;endif;whenunwork=>wash<='0';water<='1';if(tmp_low='1')thennext_state<=unwork;elsenext_state<=work;endif;endcase;endprocess;process(clk)beginif(clk'eventandclk='1')thennow_state<=next_state;endif;endprocess;endBehavioral;16、 根据真值表设计一位全加器，然后用结构的描述方法设计一个 2位加法器。（作此题人注意三个源文件都需建立到工程中且仿真只需仿真主程序即可）1.源文件半加器entityhalf_adderisport(a,b:instd_logic;s,co:outstd_logic);endhalf_adder;architectureBehavioralofhalf_adderissignalc,d:std_logic;beginprcess(a,b)beginc<=aorb;d<=anandb;co<=notd;s<=candd;endprocess;endBehavioral;2.源文件全加器entityfull_adderisport(a,b,cin:instd_logic;s,co:outstd_logic);endfull_adder;architectureBehavioraloffull_adderiscomponenthalf_adderport(a,b:instd_logic;s,co:outstd_logic);endcomponent;signalu0_co,u0_s,u1_co:std_logic;beginu0:half_adderportmap(a,b,u0_s,u0_co);u1:half_adderportmap(u0_s,cin,s,u1_co);co<=u0_cooru1_co;endBehavioral;3.源文件两位全加器主程序entityadder2bisPort(cin:in STD_LOGIC;A:in STD_LOGIC_VECTOR(1downto0);B:in STD_LOGIC_VECTOR(1downto0);s:out STD_LOGIC_VECTOR(1downto0);cout:out STD_LOGIC);endadder2b;architectureBehavioralofadder2biscomponentfull_adderPort(a:in STD_LOGIC;b:in STD_LOGIC;cin:in STD_LOGIC;s:out STD_LOGIC;co:out STD_LOGIC);endcomponent;signalz:std_logic;beginu0:full_adderportmap(A(0),B(0),cin,s(0),z);u1:full_adderportmap(A(1),B(1),z,s(1),cout);endBehavioral;17、设计4位二进制数到 BCD码（8421码）的转换器。结果由共阴极数码管显示。LIBRARYIEEE;ENTITYbcdISPORT(scanclk:INSTD_LOGIC;din:INSTD_LOGIC_VECTOR(3DOWNTO0);ledout:OUTSTD_LOGIC_VECTOR(6DOWNTO0);scanout:outintegerrange0to1);ENDbcd;ARCHITECTUREaOFbcdISsignalyh,yl,hex:integerrange0to9;signalscan:integerrange0to1;signalled:std_logic_vector(6downto0);signaly:integerrange0to15;BEGINy<=conv_integer(din);yh<=1wheny>=10andy<16else0;yl<=ywheny>=0andy<10else(y-10)wheny>=10andy<16else0;process(scanclk)beginif(scanclk'eventandscanclk='1')thenifscan=1thenscan<=0;elsescan<=1;endif;endif;endprocess;withscanselecthex<=yhwhen1,ylwhenothers;ledout<=notled;scanout<=scan;withhexselectled<="1111001"when1,"0100100"when2,"0110000"when3,"0011001"when4,"0010010"when5,"0000010"when6,"1111000"when7,"0000000"when8,"0010000"when9,"1000000"whenothers;ENDa;BCD码显示（5个数码管）LIBRARYIEEE;ENTITYbcdISPORT(scanclk:INSTD_LOGIC;din:INSTD_LOGIC_VECTOR(3DOWNTO0);ledout:OUTSTD_LOGIC_VECTOR(6DOWNTO0);scanout:outintegerrange0to4);ENDbcd;ARCHITECTUREaOFbcdISsignalscan:integerrange0to4;signalled:std_logic_vector(6downto0);signalhex,yh:std_logic;signalyl:std_logic_vector(3downto0);BEGINprocess(scanclk,din)beginif(din<="1001")thenyh<='0';yl<=din;elsif(din>"1001"anddin<="1111")thenyh<='1';yl<=din-"1010";endif;if(scanclk'eventandscanclk='1')thenifscan=4thenscan<=0;elsescan<=scan+1;endif;endif;endprocess;withscanselecthex<=yhwhen4,yl(3)when3,yl(2)when2,yl(1)when1,yl(0)whenothers;ledout<=notled;scanout<=scan;withhexselectled<="1111001"when'1',"1000000"whenothers;ENDA;18、 设计一个跑马灯控制器。一共有 4个彩灯，编号为 LED0~LED3，点亮方式为：先从左往右顺序点亮，然后从右往左，如此循环往复。LIBRARYIEEE;ENTITYlightenISPORT(CLK:INSTD_LOGIC;ledout:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDlighten;ARCHITECTUREbOFlightenISSIGNALcnt:STD_LOGIC_VECTOR(2DOWNTO0);BEGINPROCESS(CLK)BEGINIF(CLK'EVENTANDCLK='1')THENIF(cnt="110")THENcnt<="000";ELSEcnt<=cnt+'1';ENDIF;ENDIF;ENDPROCESS;WITHcntSELECTledout<="0111"WHEN"000","1011"WHEN"001","1101"WHEN"010","1110"WHEN"011","1101"WHEN"100","1011"WHEN"101","0111"WHEN"110","1111"WHENOTHERS;ENDb;19、 有四路数据输入，每路数据为 2位二进制数，根据不同的控制信号，输出相应的输入数据。同时用由共极七段数码管显示输出数据的路号libraryIEEE;entitycaiisPort(din1:in STD_LOGIC_VECTOR(0to1);din2:in STD_LOGIC_VECTOR(0to1);din3:in STD_LOGIC_VECTOR(0to1);din4:in STD_LOGIC_VECTOR(0to1);sel:in STD_LOGIC_VECTOR(0to1);ledout:out STD_LOGIC_VECTOR(6downto0);dout:out STD_LOGIC_VECTOR(0to1));endcai;architectureBehavioralofcaiisSIGNALled:STD_LOGIC_VECTOR(6downto0);begindout<=din1WHENsel="00"ELSEdin2WHENsel="01"ELSEdin3WHENsel="10"ELSEdin4WHENsel="11"ELSE(OTHERS=>'0');ledout<=NOTled;WITHselSELECTled<="1111001"WHEN"00","0100100"WHEN"01","0110000"WHEN"10","0011001"WHEN"11","1000000"WHENothers;endBehavioral;20、设计一个电磁炉控制器：火力控制有三档：煮汤、火锅、煎炒；每种操作都可以设定时间，当时间到自动停火。libraryieee;entityhuokongisport(zhutang,huoguo,jianchao:instd_logic;clk,tinghuo,reset,shi,fen,en:instd_logic;--reset

定时复位

en='1'

定时

en='0'

倒计时

shi,fen调时调分scanout:outintegerrange0to2;--clk1f:bufferstd_logic;--z0:bufferintegerrange0to9;--k:bufferstd_logic;ledout:outstd_logic_vector(6downto0);huo:outstd_logic_vector(2downto0));endhuokong;architectureaofhuokongiscomponenttjsisGENERIC(count_value:INTEGER:=9);PORT(clk,clr,en:INSTD_LOGIC;co:OUTSTD_LOGIC;count:OUTINTEGERRANGE0TOcount_value);endcomponent;signalclk1f:std_logic;signalhu:std_logic_vector(2downto0);signalk:std_logic;signaluen:std_logic;signaly:std_logic_vector(2downto0);signalz0,z10,z20,z2,z12,z22:integerrange0to9;signaly1:std_logic;signalz1,z11,z21:integerrange0to5;signalscan:integerrange0to2;signalhex:integerrange0to9;beginprocess(zhutang,huoguo,jianchao)beginif(zhutang='1')thenhu<="100";elsif(huoguo='1')thenhu<="010";elsif(jianchao='1')thenhu<="001";endif;endprocess;PROCESS(clk) --产生周期为一分钟的时钟信号variabled:integerrange0to8;BEGINIF(CLK'EVENTANDCLK='1')THENIFd=8THENd:=0;clk1f<='1';ELSEd:=d+1;clk1f<='0';ENDIF;ENDIF;ENDPROCESS;y(2)<=(y(1)andy(0));CNT1M:tjs --计时器GENERICMAP(COUNT_V ALUE=>9)PORTMAP(CLK=>CLK1f,CLR=>k,EN=>uen,CO=>y(0),COUNT=>z0);CNT10M:tjsGENERICMAP(COUNT_V ALUE=>5)PORTMAP(CLK=>CLK1f,CLR=>k,EN=>y(0),CO=>y(1),COUNT=>z1);CNT_H:tjsGENERICMAP(COUNT_V ALUE=>9)PORTMAP(CLK=>CLK1f,CLR=>k,EN=>y(2),COUNT=>z2);uen<=noten;SET1M:tjs --设定时间GENERICMAP(COUNT_V ALUE=>9)PORTMAP(CLK=>fen,CLR=>reset,EN=>en,CO=>y1,COUNT=>z10);SET10M:tjsGENERICMAP(COUNT_V ALUE=>5)PORTMAP(CLK=>fen,CLR=>reset,EN=>y1,COUNT=>z11);SET_H:tjsGENERICMAP(COUNT_V ALUE=>9)PORTMAP(CLK=>shi,CLR=>reset,EN=>en,COUNT=>z12);process(z0,z1,z2)beginif(tinghuo='1')thenk<='0';huo<="000";elsif(en='1')thenk<='0';huo<="000";elsifk='1'thenhuo<="000";elsif(en='0')thenif((z0=z10)and(z1=z11)and(z2=z22))thenk<='1';elsifk='0'thenhuo<=hu;endif;endif;endprocess;process(z0,z1,z2) --倒计时beginif(z0=0andz1=0andz2=0)thenz20<=0;z21<=0;z22<=0;elsif(z10>=z0)thenz20<=z10-z0;if(z11>=z1)thenz21<=z11-z1;z22<=z2-z12;elsez21<=z11-z1+10;z22<=z2-z12-1;endif;elsez20<=z10-z0+10;if(z11>=z1)thenz21<=z11-z1-1;z22<=z2-z12;elsez21<=z11-z1+9;z22<=z2-z12-1;endif;endif;endprocess;process(clk) --数码管选通控制信号beginif(clk'eventandclk='1')thenif(scan=2)thenscan<=0;elsescan<=scan+1;endif;endif;scanout<=scan;endprocess;hex<=z22when(scan=2anden='0')elsez21when(scan=1anden='0')elsez20when(scan=0anden='0')elsez12when(scan=2anden='1')elsez11when(scan=1anden='1')elsez10when(scan=0anden='1');withhexselect --数码管输出ledout<="0111111"WHEN0,"0000110"WHEN1,"1011011"WHEN2,"1001111"WHEN3,"1100110"WHEN4,"1101101"WHEN5,"1111101"WHEN6,"0000111"WHEN7,"1111111"WHEN8,"1101111"WHEN9,"0111111"WHENOTHERS;enda;21、血型配对指示器：供血血型和受血血型分别有当供血血型和受血血型符合要求时，T指示灯亮，否则

A、B、AB、O四种。F指示灯亮。libraryieee;entityxuexing1isport(a,b:instd_logic_vector(1downto0);tout,fout:outstd_logic);endxuexing1;architecturepeiduiofxuexing1isbeginprocess(a,b)beginif(a="00")thentout<='0';fout<='1';--00O型a：供血b：受血elsif(a="01")thenif(b="01")thentout<='0';fout<='1';--01A型elsif(b="11")thentout<='0';fout<='1';--11AB型elsetout<='1';fout<='0';endif;elsif(a="10")then--10B型if(b="10")thentout<='0';fout<='1';elsif(b="11")thentout<='0';fout<='1';elsetout<='1';fout<='0';endif;elseif(b="11")thentout<='0';fout<='1';elsetout<='1';fout<='0';--低电平亮endif;endif;endprocess;endpeidui;可变模计数器，控制信号MA和MB为00、01、10、11时计数器的模分别为3、5、7、9。（计数结果由共阴极七段数码管显示）LIBRARYIEEE;ENTITY counter ISPORT(MA,MB:INSTD_LOGIC;clk:INSTD_LOGIC;ledout:OUTSTD_LOGIC_VECTOR(6downto0));ENDcounter;ARCHITECTUREaOFcounterISSIGNALcnt:STD_LOGIC_VECTOR(3downto0);SIGNALled:STD_LOGIC_VECTOR(6downto0);BEGINPROCESS(clk)BEGINIF(clk'EVENTANDclk='1')THENIF(MA='0'ANDMB='0')THENIFcnt>="0011"THENcnt<="0001";ELSEcnt<=cnt+'1';ENDIF;ELSIF(MA='0'ANDMB='1')THENIFcnt>="0101"THENcnt<="0001";ELSEcnt<=cnt+'1';ENDIF;ELSIF(MA='1'ANDMB='0')THENIFcnt>="0111"THENcnt<="0001";ELSEcnt<=cnt+'1';ENDIF;ELSIF(MA='1'ANDMB='1')THENIFcnt>="1001"THENcnt<="0001";ELSEcnt<=cnt+'1';ENDIF;ENDIF;ENDIF;ENDPROCESS;ledout<=NOTled;WITHcntSELECTled<="1111001"WHEN"0001","0100100"WHEN"0010","0110000"WHEN"0011","0011001"WHEN"0100","0010010"WHEN"0101","0000010"WHEN"0110","1111000"WHEN"0111","0000000"WHEN"1000","0010000"WHEN"1001","1000000"WHENothers;ENDa;23设计一个跑马灯电路。共 6盏灯，编号为 LED0-LED5，这6盏灯奇偶交替着亮灭。libraryIEEE;entitypaoo1isPort(clk:in STD_LOGIC;ledout:out STD_LOGIC_VECTOR(5downto0));endpaoo1;architectureBehavioralofpaoo1isSIGNALcnt:STD_LOGIC_VECTOR(1DOWNTO0);BEGINPROCESS(CLK)BEGINIF(CLK'EVENTANDCLK='1')THENIF(cnt="01")THENcnt<="00";ELSEcnt<=cnt+'1';ENDIF;ENDIF;ENDPROCESS;WITHcntSELECTledout<="101010"WHEN"00","010101"WHEN"01","000000"WHENOTHERS;endBehavioral;24、亲子判定器：根据亲子血型关系规则，当输入的亲、子血型符合时，指示灯亮。---------------------------A 对B时有错-----------------------libraryieee;entityqinzijiandingisport(f,m,zi:instd_logic_vector(3downto0);en,clr:instd_logic;start,wrong,y:outstd_logic);endqinzijianding;architectureaofqinzijiandingisbeginprocessbeginstart<=en;ifclr='1'oren='0'theny<='0';start<='0';wrong<='0';endif;if(f="0001"andm="0001")thencaseziiswhen"0001"=>y<='1';wrong<='0';when"0010"=>y<='0';wrong<='1';when"0100"=>y<='0';wrong<='1';when"1000"=>y<='0';wrong<='1';whenothers=>wrong<='1';y<='0';endcase;elsif(f="0010"andm="0010")thencaseziiswhen"0001"=>y<='0';wrong<='1';when"0010"=>y<='1';wrong<='0';when"0100"=>y<='1';wrong<='0';when"1000"=>y<='1';wrong<='0';whenothers=>wrong<='1';y<='0';endcase;elsif(f="0100"andm="0100")thencaseziiswhen"0001"=>y<='1';wrong<='0';when"0010"=>y<='0';wrong<='1';when"0100"=>y<='1';wrong<='0';when"1000"=>y<='0';wrong<='1';whenothers=>wrong<='1';y<='0';endcase;elsif(f="1000"andm="1000")thencaseziiswhen"0001"=>y<='1';wrong<='0';when"0010"=>y<='0';wrong<='1';when"0100"=>y<='0';wrong<='1';when"1000"=>y<='1';wrong<='0';whenothers=>wrong<='1';y<='0';endcase;elsif((f="0001"andm="0010")or(f="0010"andm="0001"))thencaseziiswhen"0001"=>y<='0';wrong<='1';when"0010"=>y<='0';wrong<='1';when"0100"=>y<='1';wrong<='0';when"1000"=>y<='1';wrong<='0';whenothers=>wrong<='1';y<='0';endcase;elsif((f="0001"andm="1000")or(f="1000"andm="0001"))thencaseziiswhen"0001"=>y<='1';wrong<='0';when"0010"=>y<='0';wrong<='1';when"0100"=>y<='0';wrong<='1';when"1000"=>y<='1';wrong<='0';whenothers=>wrong<='1';y<='0';endcase;elsif((f="0001"andm="0100")or(f="0100"andm="0001"))thencaseziiswhen"0001"=>y<='1';wrong<='0';when"0010"=>y<='0';wrong<='1';when"0100"=>y<='1';wrong<='0';when"1000"=>y<='0';wrong<='1';whenothers=>wrong<='1';y<='0';endcase;elsif((f="1000"andm="0100")or(f="0100"andm="1000"))thencaseziiswhen"0001"=>y<='0';wrong<='1';when"0010"=>y<='1';wrong<='0';when"0100"=>y<='0';wrong<='1';when"1000"=>y<='0';wrong<='1';whenothers=>wrong<='1';y<='0';endcase;elsif((f="1000"andm="0010")or(f="0010"andm="1000"))thencaseziiswhen"0001"=>y<='0';wrong<='1';when"0010"=>y<='1';wrong<='0';when"0100"=>y<='1';wrong<='0';when"1000"=>y<='1';wrong<='0';whenothers=>wrong<='1';y<='0';endcase;elsif((f="0100"andm="0010")or(f="0010"andm="0100"))thencaseziiswhen"0001"=>y<='0';wrong<='1';when"0010"=>y<='1';wrong<='0';when"0100"=>y<='1';wrong<='0';when"1000"=>y<='1';wrong<='0';whenothers=>wrong<='1';y<='0';endcase;endif;endprocess;enda;25、模为7的计数器，计数步长由控制信号 A、B、C进行控制：ABC=001时，步长为 1，计数规律为：0-1-2-3-4-5-6-7-0顺序计数；ABC=010时，步长为 2，计数规律为：0-2-4-6-1-3-5-7-0顺序计数；ABC=110时，步长为1，计数规律为：0-7-6-5-4-3-2-1-0顺序计数；（计数结果由共阴极七段数码管显示）libraryIEEE;entityghisPort(clk:indin:iny:out

STD_LOGIC;STD_LOGIC_VECTOR(2downto0);STD_LOGIC_VECTOR(6downto0));endgh;architectureBehavioralofghissignalcnt:integerrange0to7;SIGNALled:std_logic_vector(6downto0);beginProcess(clk)beginifclk'eventandclk='1'thenifdin="001"thenifcnt=7thencnt<=0;elsecnt<=cnt+1;endif;elsifdin="010"thenifcnt=6thencnt<=1;elsifcnt=7thencnt<=0;elsecnt<=cnt+2;endif;elsifdin="110"thenifcnt=0thencnt<=7;elsecnt<=cnt-1;endif;endif;endif;endprocess;y<=LED;withcntselectLED<="0000110"when1,"1011011"when2,"1001111"when3,"1100110"when4,"1101101"when5,"1111101"when6,"0000111"when7,"0111111"whenOTHERS;endBehavioral;26、模为16的计数器，控制信号为MA和MB。MA和MB为00时不计数，01时加法计数器，10时减法计数器， 11时预置数功能。（计数结果由数码管显示）LIBRARYIEEE;ENTITYM16COUNTERISPORT(CLK,MA,MB,CLR:INSTD_LOGIC;YUZHI:INSTD_LOGIC_VECTOR(3DOWNTO0);LEDOUT:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDM16COUNTER;ARCHITECTUREAOFM16COUNTERISSIGNALREG:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALSET:STD_LOGIC_VECTOR(1DOWNTO0);SIGNALLED:STD_LOGIC_VECTOR(6DOWNTO0);BEGINSET<=MA&MB;PROCESS(CLK)BEGINIF(CLK'EVENTANDCLK='1')THENIFCLR='1'THENREG<=(OTHERS=>'0');ELSEIFSET="00"THENREG<=REG;ELSIFSET="01"THENREG<=REG+'1';ELSIFSET="10"THENREG<=REG-'1';ELSEREG<=YUZHI;ENDIF;ENDIF;ENDIF;ENDPROCESS;LEDOUT<=NOTLED;WITHREGSELECTLED<="1111001"WHEN"0001","0100100"WHEN"0010","0110000"WHEN"0011","0011001"WHEN"0100","0010010"WHEN"0101","0000010"WHEN"0110","1111000"WHEN"0111","0000000"WHEN"1000","0010000"WHEN"1001","0001000"WHEN"1010","0000011"WHEN"1011","1000110"WHEN"1100","0100001"WHEN"1101","0000110"WHEN"1110","0001110"WHEN"1111","1000000"WHENOTHERS;ENDA;27、4位多功能寄存器：由选择信号和控制信号进行控制。当选择信号数器，C=0为减计数器；当选择信号S=0时，将计数值移位输出：

S=1时：C=1

为加计C=1时右移串行输出， C=0时左移串行输出。（发光二极管显示）---------------------- 题目要求串出，程序为并出 ------------------------LIBRARYIEEE;ENTITYJICUNQIISPORT(CLK,S,C,CLR:INSTD_LOGIC;LED:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDJICUNQI;ARCHITECTUREAOFJICUNQIISSIGNALREG:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK)BEGINIF(CLK'EVENTANDCLK='1')THENIFCLR='1'THENREG<=(OTHERS=>'0');ELSEIFS='1'THENIFC='1'THENREG<=REG+'1';ELSEREG<=REG-'1';ENDIF;ELSEIFC='0'THENREG<=REG(2DOWNTO0)®(3);ELSEREG<=REG(0)®(3DOWNTO1);ENDIF;ENDIF;ENDIF;ENDIF;ENDPROCESS;LED<=REG;ENDA;--------------------------------- 改--------------------------------------------LIBRARYIEEE;ENTITYJICUNQIISPORT(CLK,S,C,CLR:INSTD_LOGIC;LED:OUTSTD_LOGIC);ENDJICUNQI;ARCHITECTUREAOFJICUNQIISSIGNALREG:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK)BEGINIF(CLK'EVENTANDCLK='1')THENIFCLR='1'THENREG<=(OTHERS=>'0');ELSEIFS='1'THENIFC='1'THENREG<=REG+'1';ELSEREG<=REG-'1';ENDIF;ELSEIFC='0'THENREG<=REG(2DOWNTO0)®(3);ELSEREG<=REG(0)®(3DOWNTO1);ENDIF;ENDIF;ENDIF;ENDIF;ENDPROCESS;LED<=REG(3);ENDA;28、设计一个彩灯控制系统。共 6盏灯，点亮方式为：两盏灯从两端向中间移动。entitysysisport(clk:instd_logic;led:out