《微机原理及应用实践(英文版)》Chapter 6 　BASIC INPUT AND OUTPUT INTERFACE

Chapter6BASICINPUTANDOUTPUTINTERFACE6.1Introduction6.2FunctionsofI/OInterface6.3BasicI/OInterfaceChips6.4BasicI/OPortOperation6.5DataTransferFormatsBetweenCPUandPeripherals6.6ApplicationsofBasicI/OInterfaceOBJECTIVES

Uponcompletionofthischapter,youwilllearnabout:

Theoperationofbufferedinputports

Theoperationoflatchedoutputports

I/Oaddressingspace

ThedesignoffullandpartialI/Oaddressdecoders

BasicI/Oinstruction

Basicdatatransfermode

6.1Introduction

Inchapter5,wesawhowthe8086/8088isconnectedtoitsmemorysystem.Weknewthatprogramdataandinstructionsarestoredinmemoryandaccessedoverasystembusconsistingofaddress,dataandcontrolsignals.

Manytimes,amicroprocessorisusedtocontrolaprocessthatrequiresanexchangeofdatabetweentheprocessorandtheperipheralsusedbytheprocessor.Forexample,an8086controllinganassemblylinemayreceiveinputdatafromswitchesorphotocellsthatgivethepositionofanassemblymakingitswaydowntheline.The8086willbeabletotestthestateofeachsensorbyreadingitsstatuswithaninputport.Indicatorlights,solenoids,andvideodisplayterminalsassociatedwiththeassemblylinemaybedrivenbyafewofthe8086’soutputports.

Asamatteroffact,theinput/outputunitprovidesthemicrocomputerwiththemeansforcommunicatingwiththeoutsideworld.Oftenyouhearthetermoutsideinterface.Whensomeonespeaksofthemicroprocessor’sinterface,theyaretalkinginabroadwayaboutallofthemicroprocessor’scircuitswhichareusedtoletthemicroprocessorcommunicatewithanexternaldevice.Themicroprocessor’sserialinterface,forexample,describesthemicroprocessor’sI/Oport,controllogic,dataformatconversionlogic,connector,andmaybeevencableswhichareusedtoallowthemicroprocessor-basedsystemtoconnecttoaprinter,modem,orothersimilarperipheral.

BeforewelearnaboutwhatisanI/Ointerfaceindeed,weshoulddiscusswhytheI/Ointerfaceisneeded.Themicroprocessorwouldbeabletocontroltheinput/outputdevicestostartorstop,understandthedevice’sworkingstateandthensendoutthecorrespondingcontrolsignals,whichmaketheseperipheralsactaccordinglytotherequirementsofcomputerinputoroutputdataandinformationinsequence.Inthischapter,wewilldiscussthebasicI/OandI/Ointerfaceformicroprocessor8086/8088.

6.2FunctionsofI/OInterface

6.2.1NecessityofI/OInterface

Theprocesstoexchangeinformationbetweenamicroprocessorandperipheralsisjustliketheprocesstoexchangeinformationbetweenamicroprocessorandmemory,whichisprocessedunderthecontrolofthecontrolsignalsthroughthedatabus.Butthelatteriseasierthantheformer.

Theproblemsofmessage’sswitchingbetweenmicroprocessorandperipheralsarelistedasbelow:

1) Datatransmissionspeed’sinconsistency

Usually,amicroprocessorhasamuchhigherworkingfrequencythanperipherals’,anddifferentperipheralshavedifferentworkingfrequencies.

2) Signallevel’smismatching

ThesignallevelsusedbythemicroprocessorareTTLelectrical

levels.Butmostly,theperipheralsarecomplexelectromechanicalequipmentandoftencannotbedrivenbyTTLelectricallevel.So,theperipheralsmusthavetheirownpowersystemandsignallevel.

3) Signalformats’mismatching

Thedatatransferredthroughthesystembusisusually8-bit,16-bit,or32-bitparalleldata.Butsundryperipheralsusesignalswithdifferentformats.Someuseanalogquantityandsomeuseswitchingvalue;someperipheralsareelectronicequipment,andsomeflowvoltagequantity;someadoptserialdatatransmissionmode,whileothersuseparallelmanner.

4) Timing’smismatching

Variousperipheralshaveinconsistenttimingandcontrollogiccomparedwiththemicroprocessor.

Duetothereasonsmentionedabove.TheremustbemediumcircuitstolinkperipheralsandCPU.ThecircuitiscalledI/Ointerfacecircuit,whichisbetweenthemicroprocessorandperipheralsandappliedtoassistantdatatransferandcontrollogicalcircuit.Programmableinterfacechip,I/ObusslotsinPCmainboardarebothinterfacecircuits.Withinterfacecircuits,themismatchingbetweenmicroprocessorsandperipheralscouldbesolved.Inotherwords,interfacecircuitsconnecttheperipheralstothemicroprocessorandmakethemworkinphase.6.2.2FunctionsofInterfaceCircuits

Usually,interfacecircuitshavethesebasicfunctionsasbelow:

(1) Settingdatabufferstosolvetheproblemofoutofcoordinationarousedbytheworkingfrequencyinconsistencybetweenperipheralsandmicroprocessors.

Theproblemofworkingspeed’sinconsistencycanbesolvedbysettingdatabuffer,thatis,preparesthedatathatwouldbetransferredinthebufferinadvanceandstartsthetransferwhenthetransferisneeded.Whatareusuallyusedtorealizethefunctionarebufferandlatchworkingtogetherwithproperhandshakingsignals.

Forinstance,whenthemicroprocessorworkinginhighfrequencysendsdatatoperipheralsworkinginlowfrequency,thedatacouldbesentintothelatchinadvance.Thentheperipheralreceivesthedataafteritisready.Conversely,ifthedatawouldbesenttotheprocessorfromexternaldevice,also,thedatacanbesentintoaninputregister(itisalsoakindoflatch),andthentheexternaldevicesendshandshakingsignaltoinformtheprocessortoaccessthedata.

Itisforbiddenthatsomeperipheralssenddataontothedatabusbecausethebuscouldberuinedbyacompetitionfortheuseofthedatabus.Therefore,theremustbeabufferbetweeninputregisteranddatabus.Onlywhenthechipselectsignalsentbytheprocessorarrivesatthebufferandthebufferisselectedthedatafromtheexternaldevicecouldbesentontothebus.

(2) Settingthesignalleveltransformationcircuit.

(3) Settingtheinformationconversionlogictomeettheirrequirementsofformat.

(4) SettingtimingcontrolcircuitforsynchronizingtheCPUandtheperipherals.

(5) Providingaddressdecodecircuit.

Furthermore,thereareotherfunctionsoftheinterfaces,suchasinput/outputcontrol,read/writecontrolandinterruptcontrolandsoon.Ofcourse,notalltheinterfaceshaveallthefunctionsabove.

6.3BasicI/OInterfaceChips

Themostcommonlyusedsimpleinput/outputinterfacechipsarebuffersandlatches,wewilldiscuss74LS244&74LS245ofBufferedInputPortand74LS373ofaLatchedOutputPortinthissection.

The74LS244octalbufferisatri-statedevice,meaningthatitsoutputsarecapableofgoingintoahigh-impedancestate,effectivelydisconnectingthe74LS244fromtheprocessor’sdatabus.Thehigh-impedancestatecanbethoughtofasanopenswitch.

Thisisthenormalstateofthe74LS244.Whenavalidportaddressappearsontheaddressbus,the74LS244willbeenabledbytheORgate,allowingitsoutputstoresemblethedigitaldatapresentontheeightinputs.Itisimportanttorememberthatthe74LS244isonlyenabledwhentheprocessorisreadingtheinputport!ThishappenswhentheinstructionINAL,9CHisexecuted.

A16-bitinputportrequiresanadditionoctalbufferandenablinglogic.Ifportaddress9CHistobeusedforthe16-bitinputport,thesecondbuffermustbeenabledwhenportaddress9DHisseenontheaddressbus.TheprocessorwilluseA0toenableeachhalfofthe16-bitport.

74LS245/74F245isalsoacommonlyusedbuffer.Figure6.3showsitsinternalfunctionlogicdiagram.Thedatabustransceiverblockofthebusinterfacecircuitcanbeimplementedwith74F245octalbustransceiverICs.Figure6.3(a)showsablockdiagramofthisdevice.Figure6.3(a)Blockdiagramofthe74F245octalbidirectionalbustransceiver；

(b)Circuitdiagramofthe74F245

Notethatitsbidirectionalinput/outputlinesarecalledA1throughA8andB1throughB8.LookingatthecircuitdiagraminFigure6.3(b),weseethattheGinputisusedtoenablethebufferforoperation.Ontheotherhand,thelogiclevelatthedirection(DIR)inputselectsthedirectioninwhichdataaretransferredthroughthedevice.Forinstance,logic0atthisinputsetsthetransceivertopassdatafromtheBlinestotheAlines.SwitchingDIRtologic1reversesthedirectionofdatatransfer.

Figure6.4showsacircuitthatcarriesoutthedatabustransceiverblockofthebusinterfacecircuitusingthe74F245.Forthe16-bitdatabusofthe8086microcomputer,twodevicesarerequired.HeretheDIRinputisdrivenbythesignaldatatransmit/receive(DT/R),andGissuppliedbydatabusenable(DEN).Thesesignalsareoutputsofthe8288buscontroller.Figure6.4Databustransceivercircuit

[ReadingMaterial]Anotherkeyfunctionofthedatabustransceivercircuitistobufferthedatabuslines.Thiscapabilityisdefinedbyhowmuchcurrentthedevicescansinkattheiroutputs.TheIOLratingofthe74F245is64mA.6.3.2LatchedOutputPort

Thereismoretoanoutputportthanasimplereversalofthedirectionthatdatatakesonthedatabus.Dataoutputtoaportcomesfromtheaccumulatorandisplacedontothedatabusonlyforashortperiodoftime.Wehaveonlyafewhundrednanosecondsatthemosttocapturetheoutputdatabeforeitisreplacedbyotherdata(aninstructionreadfrommemoryperhaps).3Itisnecessarytostoreacopyoftheoutputdatawhenitappears.Thisiswhyoutputportsmustcontainstorageelements.Theprocessor’scontrolsignalsareusedtotelltheoutputportcircuitrywhentostorewhatisonthedatabus.

Alatchisusedforthispurpose.The74LS373/74F373isanexampleofanoctallatchdevicethatcanbeusedtoimplementtheaddresslatchsectionofthe8086’smemoryinterfacecircuit.

AblockdiagramofthisdeviceisshowninFigure6.5(a)anditsinternalcircuitryisshowninFigure6.5(b).Notethatitacceptseightinputs:1Dthrough8D.Aslongastheclock(C)inputisatlogic1,theoutputsoftheD-byteflip-flopsfollowthelogiclevelofthedataappliedtotheircorrespondinginputs.

WhenCisswitchedtologic0,thecurrentcontentsoftheD-typeflip-floparelatched.Thelatchedinformationintheflip-flopisnotoutputatdataoutputs1Qthrough8Qunlesstheoutput-control(OC)inputofthebuffersthatfollowthelatchesisatlogic0.IfOCisatlogic1,theoutputsareinthehigh-impedancestate.Figure6.5(c)summarizesthisoperation.Figure6.5(a)BlockdiagramofanoctalD-typelatch；(b)Circuitdiagramofthe74F373(CourtesyofTexasInstrumentsIncorporated)；(c)Operationofthe74F373(CourtesyofTexasInstrumentsIncorporated)

Inthe8086microcomputersystem,the20addresslines(AD0~AD15,A16~A19)andthebankhighenablesignalBHEarenormallylatchedintheaddressbuslatch.ThecircuitconfigurationshowninFigure6.6canbeusedtolatchthesesignals.FixingOCatthe0logiclevelpermanentlyenableslatchedoutputsA0LthroughA19LandBHEL.Moreover,theaddressinformationislatchedattheoutputsastheALEsignalfromthebuscontrollerreturnstologic0–thatis,whentheCLKinputofalldevicesisswitchedtologic0.

[ReadingMaterial]Ingeneral,itisimportanttominimizethepropagationdelayoftheaddresssignalsastheygothroughthebusinterfacecircuit.Theswitchingpropertyofthe74F373latchesthatdeterminethisdelayforthecircuitofFigure6.6iscalledenable-to-outputpropagationdelayandhasamaximumvalueof13ns.

Byselectingfastlatches — thatis,latcheswithashorterpropagationdelaytime — amaximumamountofthe8086’sbuscycletimeispreservedfortheaccesstimeofthememorydevices.Inthiswayslower,lowercostmemoryICscanbeused.Theselatchesalsoprovidebufferingforthe8086’saddresslines.Theoutputsofthelatchcansinkamaximumof24mA.Figure6.6Addresslatchcircuit.6.4BasicI/OPortOperation

6.4.1I/OPortAddressMode

Inadditiontothememoryspace,8086microprocessoralsohasI/Ospace.Thisallowsittoaccessports.PortsareusedeithertobringdataintoCPUfromanexternaldevicesuchasakeyboardortosenddatafromtheCPUtoanexternaldevicesuchasaprinter.

ThesimplestmicroprocessorsystemusuallyhasmorethanoneI/Oport.ThismeansthatthemicroprocessormusthaveawaytotellwhichI/Oportitistalkingto.ThemicroprocessordoesthisbyaddressingtheI/Oportinmuchthesamewaythatitaddressesamemorylocation.

4TherearetwowaystheI/Oportcanbeconnectedtothemicroprocessorsothatitcanbeaddressed.Itcanbememory-mappedorI/O-mapped.InthisSection,wewilllookatbothtypesofI/Oportaddressmodes.

IftheI/Oportismemory-mapped,theI/Oregistersactlikeread-writeRAMattheaddressedmemorylocation.Ofcourse,theI/Oportsareaddressed(mapped)atmemorylocationswhichdonotactuallyhaveanyRAM.

Somemicroprocessors,the6802(Motorola)forexample,onlyallowmemory-mappedI/O.Thatis,theonlywayanI/Oportcanbeaddressedbythemicroprocessoristoplaceitatamemoryaddress.However,allmicroprocessorscanusethisifthedesignerfeelsthatmemory-mappedI/OisthebestwaytoaddressI/Ointheparticularsystem.

Memory-mappedI/Ohassomeadvantagesanddisadvantages.Forexample,youwillfindthatitallowstheprogrammertousethewiderangeofinstructiontypesandmemoryaddressingmodesforI/Odatatransfers.Whenmemory-mappedI/Oisused,thereisnoprogrammingdifferencebetweenanI/Odatatransferandamemorydatatransfer.

Adisadvantage,however,isthatmemory-mappedI/Oreducesthenumberofmemorylocationsavailabletotheprogrammer.IfanI/Oporthasaninputregisterandanoutputregister,thenyoumustgiveupatleasttwomemorylocations.Inmanycases,alargeblockofmemorylocationsareassignedtoI/O.Whenthishappens,theentireblockofmemorylocationsisnotavailableforROMorRAM.

[ReadingMaterial]Normally,amemorylocation,oragroupoflocations,isusedtostoreprogramdataandotherimportantinformation.Dataiswrittenintoaparticularmemorylocationandreadlaterforuse.Throughaprocesscalledmemory-mappedI/O,weremovethestoragecapabilityofthememorylocationandinsteaduseittocommunicatewiththeoutsideworld.Imaginethatyouhaveakeyboardthatsuppliesan8-bitASCⅡcode(completewithparity)wheneveryoupressakey.

Yourjobistosomehowgetthisparallelinformationintoyourcomputer.Byusingmemory-mappedI/O,amemorylocationmaybesetasidethatwhenread,willcontainthe8-bitcodegeneratedbythekeyboard.Conversely,datamaybesenttotheoutsideworldbywritingtoamemory-mappedoutputlocation.The8088CPUiscapableofperformingmemory-mappedI/Oineitherbyteorwordlengths.Allthatisrequiredisamemoryaddressdecoder,coupledwiththeappropriatebuscircuitry.

Foramemory-mappedoutputlocation,thememoryaddressdecoderprovidesaclockpulsetoanoctalflip-flopcapableofstoringtheoutputdata.Amemory-mappedinputlocationwouldusethememoryaddressdecodertoenableatri-stateoctalbuffer,placingdatafromtheoutsideworldontotheCPU’sdatabuswhenactive.Figure6.7showsthecircuitryforan8-bitmemory-mappedI/Olocation,sometimesreferredtoasamemory-mappedI/Oport.Thememoryaddressdecodermaybeusedforbothinputandoutput.

SomemicroprocessorshaveaspecialaddressingmodecalledtheI/Omappedmode,orcalledI/Oisolated.WhentheprogrammerwantstomakeanI/Odatatransfer,adifferentsetofthemicroprocessor’scontrollinesisused.TheseI/Ocommands,likethememorycommands,usethemicroprocessor’saddressbusanddatabus,butthereisonedifference.ThesemicroprocessorshaveaspecialI/OcontrollineorsetofI/Ocontrollines.Figure6.7memory-mappedI/Ocircuitry

ControllinessignaltheexternalmicroprocessorsupportlogicthatthedatatransferistobewithmemoryorwithanI/Odevice.Usually,thereisonelinetotellthelogicthatthetransferisanI/Otransferandtheotherthattellsthelogicthatthetransferisamemorytransfer.Whenthecontrollinessignalamemorydatatransfer,theI/Osupportlogicisdisabled.Likewise,whenthecontrollinessignalanI/Otransfer,thememorysupportlogicisdisabled.

OftenthemicroprocessordoesnothaveasmanyI/Olocationsasithasmemorylocations.Forexample,onecommon8-bitmicroprocessorhas64K(65,536)memorylocations.However,itonlyhas256I/Olocations.WhenanI/Ooperationhappens,the8-bitmicroprocessorusesthelower8linesofthe16linesinitsaddressbus.DuringadatatransferwithanI/Olocation,thedataistransferredoverthe8-bitdatabusjustasitisduringadatatransferwithamemorylocation.Figure6.8showsthetwoformsthatmicroprocessorsusetocommunicatewithmemoryandI/O.6.4.2HandshakingSynchronizationofI/OInterface

Insomeapplications,themicrocomputermustsynchronizetheinputoroutputofinformationtoaperipheral.Twoexamplesofinterfacesthatmayrequireasynchronizeddatatransferareserialcommunicationsinterfaceandaparallelprinterinterface.

SometimesitisnecessaryaspartoftheI/OsynchronizationprocessfirsttopollaninputfromanI/Odeviceand,afterreceivingtheappropriatelevelatthepollinput,toacknowledgethisfacttothedevicewithanoutput.Thistypeofsynchronizationisachievedbyimplementingwhatisknownashandshakingaspartoftheinput/outputinterface.

Figure6.9(a)showsaconceptualviewoftheinterfacebetweentheprinterandaparallelprinterport.Therearethreegeneraltypesofsignalsattheprinterinterface:data,control,andstatus.Thedatalinesaretheparallelpathsusedtotransferdatatotheprinter.

Transfersofdataoverthisbusaresynchronizedwithanappropriatesequenceofcontrolsignals.However,datatransferscanonlytakeplaceiftheprinterisreadytoacceptdata.Printerreadinessisindicatedthroughtheparallelinterfacebyasetofsignalscalledstatuslines.ThisinterfacehandshakingsequenceissummarizedbytheflowchartshowninFigure6.9(b).

Theprinterisattachedtothemicrocomputersystemataconnectorknownastheparallelprinterport.OnaPC,a25-pinconnectorisusedtoattachtheprinter.Figure6.9(c)showstheactualsignalssuppliedatthepinsofthisconnector.Notethattherearefivestatussignalsavailableattheinterface,andtheyarecalledAck,Busy,PaperEmpty,Select,andError.Inaparticularimplementationonlysomeofthesesignalsmaybeused.Forinstance,tosendacharactertotheprinter,thesoftwaremaytestonlytheBusysignal.Ifitisinactive,itmaybeasufficientindicationtoproceedwiththetransfer.

Letusnowlookatthesequenceofeventsthattakeplaceattheparallelprinterinterfacewhendataareoutputtotheprinter.Figure6.10(c)isaflowchartofasubroutinethatperformsaparallelprinterinterfacecharacter-transferoperation.FirsttheBUSYinputoftheparallelprinterinterfaceistested.Notethatthisisdonewithapollingoperation.Thatis,theCPUteststhelogiclevelofBUSYrepeatedlyuntilitisfoundtobeatthenot-busylogiclevel.BUSYmeansthattheprinteriscurrentlyprintingacharacter.

Ontheotherhand,notbusysignalsthattheprinterisreadytoreceiveanothercharacterforprinting.Afterfindinganot-busycondition,acountofthenumberofcharacterintheprinterbuffer(microprocessormemory)isread;abyteofcharacterdataisreadfromtheprinterbuffer;thecharacterisoutputtotheparallelinterface;andthenapulseisproducedat

.

Thispulsetellstheprintertoreadthecharacteroffthedatabuslines.TheprinterisagainprintingacharacterandsignalsthisfactatBUSY.Thehandshakesequenceisnowcomplete.Nowthecountthatrepresentsthenumberofcharactersinthebufferisdecrementedandcheckedtoseeifthebufferisempty.Ifempty,theprintoperationiscomplete.Otherwise,thecharactertransfersequenceisrepeatedforthenextcharacter.6.4.3BasicI/OInstructions

Input/outputoperationsareperformedbythe8088and8086microprocessorsthatemployisolatedI/OusingspecialinputandoutputinstructionstogetherwiththeI/Omappedportaddressingmodes.Theseinstructions,in(IN)andout(OUT),arelistedinTable6.1.Theirmnemonicsandformatsareprovidedtogetherwithabriefdescriptionoftheiroperations.

NotethattherearetwodifferentformsofINandOUTinstructions:thedirectI/OinstructionsandvariableI/Oinstructions.Eitherofthesetwotypesininstructionscanbeusedtotransferabyteorwordofdata.AlldatatransferstakeplacebetweenanI/OdeviceandtheCPU’saccumulatorregister.Forthisreason,thismethodofperformingI/OisknownasaccumulatorI/O.BytetransfersinvolvetheALregister,andwordtransferstheAXregister.

Infact,specifyingALasthesourceordestinationregisterinanI/Oinstructionindicatesthatitcorrespondstoabytetransfer.Thatis,byte-wideorword-wideinput/outputisselectedbyspecifyingtheaccumulator(Acc)intheinstructionasALorAX,respectively.

Anexampleistheinstruction

INAL,0FEH

Executionofthisinstructioncausesthecontentsofthebyte-wideI/OportataddressFE16oftheI/OaddressspacetobeinputtotheALregister.Thisdatatransfertakesplaceinoneinputbuscycle.

5ThedifferencebetweenthedirectandvariableI/OinstructionsliesinthewayinwhichtheaddressoftheI/Oportisspecified.WejustsawthatfordirectI/Oinstructionsan8-bitaddressisspecifiedaspartoftheinstruction.Ontheotherhand,thevariableI/Oinstructionsusea16-bitaddressthatresidesintheDXregisterwithintheCPU.ThevalueinDXisnotanoffset.ItistheactualaddressthatistobeoutputonAD0throughAD7andA8throughA15duringtheI/Obuscycle.Sincethisaddressisafull16bitsinlength,variableI/Oinstructionscanaccessportslocatedanywhereinthe64K-byteI/Oaddressspace.

WhenusingeithertypeofI/Oinstruction,thedatamustbeloadedintoorremovedfromtheALorAXregisterbeforeanotherinputoroutputoperationcanbeperformed.InthecaseofvariableI/Oinstructions,theDXregistermustbeloadedwiththeaddress.Thisrequiresexecutionofadditionalinstructions.Forinstance,theinstructionsequence

MOV DX,0A000H

IN AL,DX

MOV BL,AL

meansthatinputsthecontentsofthebyte-wideinputportatA00016oftheI/OaddressspaceintoALandthensavesitinBL.

6.5DataTransferFormatsBetweenCPU

andPeripherals

Datatransfersbetweenthe8088/8086andI/Odevicesareperformedoverthedatabus.Datatransferringtobyte-wideI/Oportsalwaysrequireonebuscycle.BytedatatransferstoaportareperformedoverbuslinesD0throughD7.Wordtransfersalsotakeplaceoverthedatabus,D0throughD7.However,thistypeofoperationisperformedastwoconsecutivebyte-widedatatransfersandtakestwobuscycles.6.5.1PollingRoutineMode

Apollingroutineisverysimple.Themicroprocessor’ssoftwaresimplycheckseachoftheI/Odeviceseverysooften.Duringthischeck,themicroprocessorteststoseeifanydeviceneedsservicing.Forexample,aftercompletingabasiccalculationthemicroprocessorcallsthepollingsubroutine.ThepollingroutinemightlookliketheoneshowninFigure6.11.Figure6.11Apollingroutine(ThisprogramchecksthestatusregisterofeachI/Odeviceintheprogram’slist.IftheI/Odevice’sservicerequestbitisset,theprogramcallsaserviceroutineforthatdevice.)

ThisisasimpleprogramwhichservicesI/Oports01,02,and03.Onceweenterthepollingroutine,wetransferI/Oport01’sstatustotheaccumulator.TheI/Oport’sstatusisfoundinaspecialstatusregisterlocatedattheI/Oportwiththeinputandoutputdataregisters.DifferentbitsinthisregisteraresetorclearedtoshowthestatusoftheI/Oporthardware.Onebit,theservicerequestbit,issetwhentheI/Oportneedsservice.IntheI/Opollingroutine’sdecisionblock,wetestthisstatusregistertoseeiftheservicerequestbitisset.Ifitis,I/Oport01’sserviceroutineiscalled.WhenwereturnfromtheI/Oport’sserviceroutine,wereturntothepollingroutine.

Thepollingroutinemovesontotestport02afteroneoftwoactionsiscomplete:iftheport01servicerequestbitisnotset,orifthecalltotheI/Oserviceroutineiscomplete.Eitheractioncausesthemicroprocessortotestport02’sstatusregistertoseeifitsservicerequestbitisset.

ThistestandserviceprocedurecontinuesuntilalltheI/OportstatusregistersaretestedandalltheI/Oportsneedingserviceareserviced.Oncethisisdone,themicroprocessorcontinuestoexecutethenormalprograms.

ThepollingroutineassignsprioritiestothedifferentI/Odevices.Again,lookattheFigure6.13.Oncethepollingroutine

isstarted,theservicerequestbitatport01isalwayscheckedfirst.Onceport01ischecked,port02ischecked,andthenport03.However,theordercanbechangedbysimplychangingthepollingroutine.Tochangeit,youonlyneedtochangetheI/Oportnumbersinthegetstatusregisterinstructions.

ThepollingroutineisstartednotbytheI/Odevicebutbythesoftware.Whenthemainprogramreachesthepollingroutinesubroutinecall,thepollingbegins.PollingroutinescannotbeusedunlesstheI/Odevicescanwaitforservice.6.5.2InterruptMode

TheotherwaytostartanI/OdeviceservicedisforthisI/Odevicetoaskforservice.ItdoesthisbyusingaspecialmicroprocessorI/Oportcalledtheinterrupt.Theinterruptisaspecialinputtothemicroprocessor’scontrollogic.Interruptsindifferentmicroprocessorsoperateinslightlydifferentways.However,theyallhavethesameresult.

Whentheinterruptinputisasserted(asignalissenttotheinterruptinput),aspecialsequenceinthecontrollogicbegins.Itmakessuretha