六十秒倒计时

六十秒倒计时一、分化设计要求二、设计计划路线三、软件设计四、调试五、实现一、分化设计要求1、实现数码管连续显示数字2、实现在数码管上显示组合003、在数码管上逆序显示00至59这60种组合4、实现60种组合每秒钟按相应数字显示5、由于硬件要求是数码管所有相同段并联，所以要求利用计数分时扫描的方法二、设计计划路线1、采用层次性设计中自顶向下混合设计。释义：所谓自顶向下的设计方法，是指设计电子系统先从系统最抽象的层次出发，作高层次仿真，经过仿真验证后再经整体规划(FloorPlanning)将系统行为操作分为多个子系统。由刚才的设计要求可知我们需要译码输出模块，以显示数不断变化的数字，并需要计数器产生60种相对于译码器的输入信号，我们这里采用减计数器模块，计数器需要1Hz脉冲，所以要有3MHz转1Hz的分频器计数分时扫描模块由于以下硬件电路的接法，所以采用计数分时，即用计数器的不同计数区段来区分每一显示位的显示，要求每位显示时间小于24分之1秒，这样在视觉上可以达到组数码管同时显示不同的数；（利用视觉暂留）3、软件设计LIBRARYieee;USEieee.std_logic_1164.all;useieee.std_logic_unsigned.all;--EntityDeclarationENTITYcounter60IS --{{ALTERA_IO_BEGIN}}DONOTREMOVETHISLINE! PORT ( reset:INSTD_LOGIC; en:INSTD_LOGIC; clk1h:INSTD_LOGIC; q:OUTSTD_LOGIC_VECTOR(5downto0) ); --{{ALTERA_IO_END}}DONOTREMOVETHISLINE!

ENDcounter60;减计数器模块ARCHITECTUREcounter60_architectureOFcounter60ISsignalq1:STD_LOGIC_VECTOR(5downto0);

BEGINprocess(clk1h,en,reset)beginifen='1'thenif(clk1h'eventandclk1h='1')then

ifq1>0thenq1<=q1-1;elseq1<="111011";endif;endif;

endif;endprocess;q<=q1;ENDcounter60_architecture;LIBRARYieee;USEieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;--EntityDeclarationENTITYfpqIS PORT ( clk3m:INSTD_LOGIC; clk1:OUTSTD_LOGIC );

ENDfpq;ARCHITECTUREfpq_architectureOFfpqIS signalfp1:std_logic; signaltout:integerrange0to30000;signaltout1:integerrange0to100;signaltout2:std_logic;

BEGINprocess(clk3m)beginif(clk3m'eventandclk3m='1')theniftout>=29999thentout<=0;elsetout<=tout+1;endif;iftout<=14999thentout2<='1';elsetout2<='0';endif;endif;endprocess;process(tout2)beginif(tout2'eventandtout2='1')theniftout1>=99thentout1<=0;elsetout1<=tout1+1;endif;iftout1<=49thenfp1<='1';elsefp1<='0';

endif;endif;endprocess;clk1<=fp1;ENDfpq_architecture;分频器模块LIBRARYieee;USEieee.std_logic_1164.all;useieee.std_logic_unsigned.all;--EntityDeclarationENTITYjishu1000IS --{{ALTERA_IO_BEGIN}}DONOTREMOVETHISLINE! PORT ( rst:INSTD_LOGIC; clk100m:INSTD_LOGIC; kai:INSTD_LOGIC; s:OUTSTD_LOGIC_VECTOR(9downto0) ); --{{ALTERA_IO_END}}DONOTREMOVETHISLINE!

ENDjishu1000;--ArchitectureBodyARCHITECTUREjishu1000_architectureOFjishu1000IS

signals1:std_logic_vector(9downto0);

BEGINprocess(clk100m,rst,kai)beginifkai='1'then

ifclk100m'eventandclk100m='1'thenifs1<"0100000000"thens1<=s1+1;elses1<="0000000000";endif;endif;endif;endprocess;s<=s1;ENDjishu1000_architecture;加计数器LIBRARYieee;USEieee.std_logic_1164.all;useieee.std_logic_unsigned.all;ENTITYyimaIS PORT ( i:INSTD_LOGIC_VECTOR(5downto0); de:OUTSTD_LOGIC_VECTOR(6downto0); rj:outSTD_LOGIC; rj60:outstd_logic; jishu100:inSTD_LOGIC_VECTOR(9downto0);

dig:OUTSTD_LOGIC_VECTOR(1downto0) );

ENDyima;ARCHITECTUREyima_architectureOFyimaISsignalrj1:STD_LOGIC;signalr:std_logic;beginprocess(i,jishu100)begincaseiiswhen"111011"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")then

de<="0010000";dig<="10";--9endif;endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5endif;when"111010"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")thende<="0000000";dig<="10";--8endif;endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5endif;when"111001"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")thende<="1111000";dig<="10";--7endif;

when"110111"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")thende<="0010010";dig<="10";--5endif;endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5endif;

when"110110"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")thende<="0011001";dig<="10";--4endif;endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5

endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5endif;when"111000"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")thende<="0000010";dig<="10";--6endif;endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5endif;

when"110101"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")thende<="0110000";dig<="10";--3endif;endif;if(jishu100<="0010000000")thende<="0010010";dig<="01";--5endif;when"110100"=>if(jishu100>="0010000000")thenif(jishu100<="0100000000")then