双口RAM应用实例

ffA4d2Ws——喳2—3Ui—A='、C1Hi鼻4son='、C1Hi鼻4son5-A41■A8AV5g1YUiiHv4西AMVJ"m©CTA1RAM用干扰大，电路可靠性低，难以满足高速数据采集工作的要求。应用FPGA可以把成进一片芯片中，高集成性增强了系统的稳定性，为高速数据采集提供了理想的解RAM用。河「育谏据宰荽辛净股街iL业cut业*——n>p.~!!•■三tA4JVJM$i心w数器实现，计数频率与ADCLK、WRCLK一致以保证数据写入时序的正确性。写操时钟产生。停止采样时AD_STOP有效,写地址发生器停止计数，同时停止对地址发生器单元一般用(VHDL)语言编程实现，然后生成符号文件RAM_CONTROLLQc=klflta;aa:be莒intfCLR=1'thenWIUWclsif(CLK'cYeniandCLK-DihenifAD^STOP-FihcaWRc=tr.ifthenelsed对砂I;V/R<=CLKAndif；endif,endif;endpJDcessaa:M行数据缓存，由于其已经把地址发生部分集成在模块单元内,因此省去了一部分程序D到该总线上，否则会产生总线冲突，引起芯片损坏。解决这个问题就需要增加电FPGAISP在线更新、升级容易等特点，较为理想的系统及电路实现方法。列。因此，在FPGA中实现各种存储器，如单/双端口RAM、单/双端口ROM、先U利用库函数构造双端口RAM系列芯片；而下文将要详细介绍的参数化双端口RAMmegalpm)中，包括各种参数化运算模块(加、减、乘、除)、参数化存储模块(单、双端口RAM、ROM、FIFO、比较器模块等等。库中的这些元件功能逻辑描述经过了优化验证，是数的极好选择。mega-lpm库中共有五种参数化双端口RAM模块：ALTDPRAM、LPM_RAM_DP、RAMLPMRAMDP种参数的取舍、参数设置和组合，再结合读写控制逻辑就可以构造出设计需要的存储器模块。双端口1.存储器映像方式。该方式可以随意对存储器的任何单元进行读写操作。其主要应于用多CPU和数据总线2.顺序写方式。该方式对RAM的写操作只能顺序写入。这种情况适用于对象特性与我用的FPGA芯片是EP1C6Q240C6，其内部静态RAM容量Upto294,912RAMbits(36,864psystranslateofftimescalepspssynopsystranslateonmoduleatawrenwraddressrdaddresswrclockrdclockwraclrrdaclrqwire[31:0]sub_wire0;wire[31:0]q=sub_wire0[31:0];wren;ddressdresswrclock;wr_aclr;altsyncramaltsyncram_component(.wren_a(wren),.aclr0(wr_aclr),.clock。(wrclock),.aclr1(rd_aclr),.clockl(rdclock),.address_a(wraddress),.address_brdaddressdataadata),.q_b(sub_wire0)//synopsystranslate_off.addressstall_b(),.byteena_a(),.byteena_b(),.clocken0(),.clocken1(),.data_b(),.q_a(),.rden_b(),.wren_b()//synopsystranslate_on)；aramaltsyncram_ended_device_family="Cyclone",altsyncram_component.operation_mode="DUAL_PORT",altsyncram_component.width_a=1,altsyncram_component.widthad_a=14,ponentnumwordsaAaltsyncram_component.width_b=32,altsyncram_component.widthad_b=9,altsyncram_component.numwords_b=512,//2A9=512altsyncram_component.lpm_type="altsyncram",altsyncram_component.width_byteena_a=1,altsyncram_component.outdata_reg_b="UNREGISTERED",altsyncram_component.indata_aclr_a="CLEAR0",altsyncram_component.wrcontrol_aclr_a="CLEAR0",altsyncram_component.address_aclr_a="CLEAR0",altsyncram_component.address_reg_b="CLOCK1",altsyncram_component.address_aclr_b="CLEAR1",altsyncram_component.outdata_aclr_b="NONE",altsyncram_component.power_up_uninitialized="FALSE";le//双端口RAM勺设计与测试(verilog)以下是用verilog语言写的同步双端口设计文件(来自Actel官方文件中)编程风格也不错，该文档中注释的相当明确测试写的比设计长多了，写的很好值得学习，也可以直接用在你的设计中'timescale1ns/100psparameterwidth=8;//buswidthparameteraddr=8;//#ofaddrlinesparameternumvecs=20;//actualnumberofvectorsparameterClockper=1000;//100nsperiodegwidthDataregaddr0]WAddress,RAddress;regClock,WE,RE,rst;//additionrstreg[width-1:0]data_in[0:numvecs-1];reg[width-1:0]data_out[0:numvecs-1];wire[width-1:0]Q;gerijknumerrorsramudataData),.q(Q),.clk(Clock),renREwaddrWAddressraddr(//sequentialtestpatternsenteredatnegedgeClockdata_in[0]=8'h00;data_out[0]=8'hxx;data_in[1]=8'h01;data_out[1]=8'hxx;data_in[2]=8'h02;data_out[2]=8'hxx;data_in[3]=8'h04;data_out[3]=8'hxx;data_in[4]=8'h08;data_out[4]=8'hxx;data_in[5]=8'h10;data_out[5]=8'hxx;data_in[6]=8'h20;data_out[6]=8'hxx;data_in[7]=8'h40;data_out[7]=8'hxx;data_in[8]=8'h80;data_out[8]=8'hxx;data_in[9]=8'h07;data_out[9]=8'h01;data_in[10]=8'h08;data_out[10]=8'h02;data_in[11]=8'h09;data_out[11]=8'h04;data_in[12]=8'h10;data_out[12]=8'h08;data_in[13]=8'h11;data_out[13]=8'h10;data_in[14]=8'h12;data_out[14]=8'h20;data_in[15]=8'h13;data_out[15]=8'h40;data_in[16]=8'h14;data_out[16]=8'h80;data_in[17]=8'haa;data_out[17]=8'h80;data_in[18]=8'h55;data_out[18]=8'haa;data_in[19]=8'haa;data_out[19]=8'h55;WE=0;WAddress=0;#200rst=1;//thererstresettoram#200rst=0;always#(Clockper/2)Clock=~Clock;#2450WE=1;#8000WE=0;#8000RE=0;WE=1;#1000RE=1;50;for(k=0;k<=width;k=k+1)#1000WAddress=k;WAddress=0;50;for(j=0;j<=width;j=j+1)#1000RAddress=j;$display("\nBeginningSimulation...");//skipfirstrisingedgefor(i=0;i<=numvecs-1;i=i+1)negedgeClock//applytestpatternatnegedgeData=data_in;posedgeClock#450;//45nslater//checkresultatposedge+45ns$display("Pattern#%dtime%d:WE=%bWaddr=%h;RE=%b;Raddr=%h;Data=%h;ExpectedQ=%h;ActualQ=%h”,i,$stime,WE,WAddress,RE,RAddress,Data,dataoutQ);ifQ!==data_out)$display("**Error");numerrors=numerrors+1;rrors$display("Good!EndofGoodSimulation.");ifnumerrors1)y"%0dERRORS!EndofFaultySimulation.",y"1ERROR!EndofFaultySimulation.");#1000$finish;//after100nslater为了方便，我将其设计代码也放在这儿，你可以直接用综合和仿真timescale1ns/100psffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff〃““TF““TFTF““TF““TrTrmTTr”“rTTTTTTTTTTTTTTTTTTTT““TF““TFTF““TF““F“”//ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff//#ActiveHighwriteenable(WE)//#ActiveHighreadenable(RE)//#Risingclockedge(Clock)//ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff〃““TF““TFTF““TF““TrTrmTTr”“rTTTTTTTTTTTTTTTTTTTT““TF““TFTF““TF““F“”//ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffRAddress);eterwidthmeterdepthteraddrckWEREnputaddrWAddressRAddressdthDataoutputwidth:0]Q;regwidthmemdata[depth-1:0];//ftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftft//“，‘7T7T7T7T7T7T7T7T7T7T7T7T7T7T，，“TFTF“"TF““TF““TFTF“““TF7T7T“““7T7T//ffffffff//ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff//ftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftftft//“，ysposedgeClockmem_data[WAddress]=#1//ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffysposedgeClockmem_data[WAddress]=#1‘7T7T7T7T7T7T7T7T7T7T7T7T7T7T，，“TFTF“"TF““TF““TFTF“““TF7T7T“““7T7T//#ReadFunctionalSectiontititititititititititititititititititititititititi