深入浅出玩转fpga随书光盘教程qts qii

©November2008Al

Corporation

QuartusIIHandbookVersion8.1Volume3:Verification

QuartusIIHandbookVersion8.1Volume3:Verification

©November2008Al

Corporation

7.TheQuartusIITimeQuest

Timingyzer

QII53018-8.1.0

Introduction

TheQuartus®IITimeQuestTiming yzerisapowerfulASIC-styletiming ysistoolthatvalidatesthetimingperformanceofalllogicinyourdesignusinganindustry-standardconstraint, ysis,andreportingmethodology.Usethe

QuartusIITimeQuestTiming yzer’sGUIorcommand-lineinterfacetoconstrain,yze,andreportresultsforalltimingpathsinyourdesign.

BeforerunningtheQuartusIITimeQuestTimingyzer,youmustspecifyinitialtimingconstraintsthatdescribetheclockcharacteristics,timingexceptions,andsignaltransitionarrivalandrequiredtimes.YoucanspecifytimingconstraintsintheSynopsysDesignConstraints(.sdc)fileformatusingtheGUIorcommand-lineinterface.TheQuartusIIFitteroptimizesthecementoflogictomeetyourconstraints.

Duringtiming ysis,theQuartusIITimeQuestTiming yzer yzesthetimingpathsinthedesign,calculatesthepropagationdelayalongeachpath,checksfortimingconstraintviolations,andreportstimingresultsasslackintheReportpaneandintheConsolepane.IftheQuartusIITimeQuestTimingyzerreportsanytimingviolations,youcancustomizethereportingtoviewprecisetiminginformationaboutspecificpaths,andthenconstrainthosepathstocorrecttheviolations.Whenyourdesignis oftimingviolations,youcanbeconfidentthatthelogicwilloperateasintendedinthetargetdevice.

TheQuartusIITimeQuestTiming yzerisacompletestatictiming ysistoolthatyoucanuseasasign-offtoolforAl ®FPGAsand®ASICs.

Thischaptercontainsthefollowingsections:

“GettingStartedwiththeQuartusIITimeQuestTimingyzer”

“CompilationFlowwiththeQuartusIITimeQuestTimingyzerGuidelines”onpage7–2

“TimingysisOverview”onpage7–5

“TheQuartusIITimeQuestTimingyzerFlowGuidelines”onpage7–21

“TheQuartusIITimeQuestTimingyzerFlowGuidelines”onpage7–21

“Collections”onpage7–22

“SDCConstraintFiles”onpage7–24

“ClockSpecification”onpage7–26

“I/OSpecifications”onpage7–40

“TimingExceptions”onpage7–44

“ConstraintandExceptionRemoval”onpage7–51

“TimingReports”onpage7–52

“TimingysisFeatures”onpage7–73

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Chapter7:TheQuartusIITimeQuestTiming

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Chapter7:TheQuartusIITimeQuestTiming

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GettingStartedwiththeQuartusIITimeQuestTiming yzer

“TheTimeQuestTiming yzerGUI”onpage7–78

“Conclusion”onpage7–88

f FormoreinformationabouttheTimeQuestTiming yzerandtheSOPCBuilder,refertoVolume4:SOPCBuilderintheQuartusIIHandbook.

GettingStartedwiththeQuartusIITimeQuestTiming yzer

TheQuartusIITimeQuestTiming yzercaterstotheneedsofthemostbasictothemostadvanceddesignsforFPGAs.

ThissectionprovidesabriefoverviewoftheQuartusIITimeQuestTiming yzer,includingthenecessarystepstoproperlyconstrainadesign,performafull

ce-and-route,andperformreportingonthedesign.

SettingUptheQuartusIITimeQuestTiming yzer

TheQuartusIIsoftwareversion7.2andlatersupportstwonativetiming ysistools:QuartusIITimeQuestTiming yzerandQuartusIIClassicTiming yzer.

WhenyouspecifytheQuartusIITimeQuestTiming yzerasthedefaulttimingysistool,theQuartusIITimeQuestTiming yzerguidestheFit ndyzestimingresultsaftercompilation.

TospecifytheQuartusIITimeQuestTiming yzerasthedefaulttiming yzer,ontheAssignments ,clickSettings.IntheSettingsdialogbox,intheCategorylist,selectTimingysisSettingsandturnonUseTimeQuestTiming yzerduringcompilation.

ToaddtheTimeQuesticontotheQuartusIItoolbar,ontheTools ,clickCustomize.IntheCustomizedialogbox,clicktheToolbarstab,turnonProcessing,andclickClose.

CompilationFlowwiththeQuartusIITimeQuestTiming yzerGuidelines

WhenyouenabletheQuartusIITimeQuestTiming yzerasthedefaulttimingyzer,everythingfromconstraintvalidationtotimingverificationisperformedby

theQuartusIITimeQuestTimingyzer.Figure7–1showsthe mendeddesignflowstepsto izeandleveragethebenefitstheQuartusIITimeQuestTiming yzer.Detailsabouteachstepareprovidedafterthefigure.

©November2008Al

Corporation

QuartusIIHandbookVersion8.1Volume3:Verification

QuartusIIHandbookVersion8.1Volume3:Verification

©November2008Al

Corporation

CompilationFlowwiththeQuartusIITimeQuestTiming yzerGuidelines

PerformInitialCompilation

CreateQuartusIIProjectandSpecifyDesignFiles

PerformCompilation

SpecifyTimingRequirements

Figure7–1.DesignFlowwiththeQuartusIITimeQuestTimingyzer

VerifyTiming

CreateQuartusIIProjectandSpecifyDesignFiles—Createsaprojectbeforeyoucancompiledesignfiles.InthisstepyouspecifythetargetFPGA,anyEDAtoolsusedinthedesigncycle,andalldesignfiles.

Youc somodifyexistingdesignfilesfordesignoptimizationandaddadditionaldesignfiles.Forexample,youcanaddHDLfilesorschematicstotheproject.

PerformInitialCompilation—Createsaninitialdesigndatabasebeforeyouspecifytimingconstraintsforyourdesign.PerformysisandSynthesistocreateapost-mapdatabase,orperformafullcompilationtocreateapost-fitdatabase.

Creatingapost-mapdatabasefortheinitialcompilationisfasterthancreatingapost-fitdatabase.Apost-mapdatabaseissufficientfortheinitialdatabase.

Creatingapost-fitdatabaseis mendedonlyifyoupreviouslycreatedandspecifiedan.sdcfilefortheproject.Apost-mapdatabaseissufficientfortheinitialcompilation.

SpecifyTimingRequirements—TimingrequirementsguidetheFitsitcesandroutesyourdesign.

Youmusten lltimingconstraintsandexceptionsinan.sdcfile.Thisfilemustbeincludedaspartoftheproject.Toaddthisfiletoyourproject,ontheProject

,clickAdd/RemoveFilesinProjectandaddthe.sdcfileintheFilesdialog

box.

PerformCompilation—Synthesizes,ces,androutesyourdesignintothetargetFPGA.

Whencompilationiscomplete,theTimeQuestTiming yzergeneratessummaryclocksetupandclockhold,recovery,andremovalreportsforalldefinedclocksinthedesign.

RunningtheQuartusIITimeQuestTiming yzer

VerifyTiming—VerifiestiminginyourdesignwiththeQuartusIITimeQuestTiming yzer.Referto“TheQuartusIITimeQuestTimingyzerFlowGuidelines”onpage7–21.

RunningtheQuartusIITimeQuestTiming yzer

YoucanruntheQuartusIITimeQuestTiming yzerinoneofthefollowingmodes:

DirectlyfromtheQuartusIIsoftware

Stand-alonemode

Command-linemode

Thissectiondescribeseachofthemodes,andthebehavioroftheQuartusIITimeQuestTimingyzer.

DirectlyfromtheQuartusIISoftware

ToruntheQuartusIITimeQuestTiming yzerfromtheQuartusIIsoftware,ontheTools ,clickTimeQuestTiming yzer.TheQuartusIITimeQuestTiming

yzerisavailableafteryouhavecreatetabaseforthecurrentproject.Thedatabasecanbeeitherapost-maporpost-fitdatabase;perform

ysisandSynthesistocreateapost-mapdatabase,orafullcompilationtocreateapost-fitdatabase.

1 Af databaseiscreated,youcancreateatimingnetlistbasedonthatdatabase.Ifyoucreateapost-mapdatabase,youcannotcreateapost-fittimingnetlistintheQuartusIITimeQuestTiming yzer.

WhenyoulaunchtheTimeQuestTiming yzerdirectlyfromtheQuartusIIsoftware,thecurrentprojectopensbydefault.

Stand-AloneMode

ToruntheQuartusIITimeQuestTiming yzerinstand-alonemode,typethefollowingcommandatthecommandprompt:

quartus_stawr

Instand-alonemode,youcanperformstatic ysisonanyprojectthatcontainseitherapost-maporpost-fitdatabase.Toopenaproject,double-clickOpenProjectintheTaskspane.

Command-LineMode

Usecommand-linemodeforeasyintegrationwithscripteddesignflows.Usingthecommand-linemodeavoidsin ctionwiththeuserinterfaceprovidedbytheQuartusIITimeQuestTiming yzer,butallowstheautomationofeachstepofthestatictiming ysisflow.Table7–1providesasummaryoftheoptionsavailableinthecommand-linemode.

Chapter7:TheQuartusIITimeQuestTiming

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Timing

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Chapter7:TheQuartusIITimeQuestTiming

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Timing

ysisOverview

©November2008Al

Corporation

QuartusIIHandbookVersion8.1Volume3:Verification

QuartusIIHandbookVersion8.1Volume3:Verification

©November2008Al

Corporation

Table7–1.SummaryofCommandLineOptions

CommandLineOption

Description

-h|--help

Provideshelpinformationonquartus_sta.

-t<scriptfile>|

--script=<scriptfile>

Sourcesthe<scriptfile>.

-s|--s

Enterssmode.

--tcl_eval<tclcommand>

EvaluatestheTclcommand<tclcommand>.

--do_report_timing

Forallclocksinthedesign,runthefollowingcommands:report_timing-npaths1-to_clock$clockreport_timing-setup-npaths1-to_clock$clockreport_timing-hold-npaths1-to_clock$clockreport_timing-recovery-npaths1-to_clock$clock

report_timing-removal-npaths1-to_clock$clock

--_dat

stheDelayAnnotatortoannotatethenewdelaysfromtherecentlycompileddesigntothecompilerdatabase.

--lower_priority

Lowersthecomputingpriorityofthequartus_staprocess.

--post_map

Usesthepost-mapdatabaseresults.

--qsf2sdc

ConvertsassignmentsfromtheQuartusIISettingsFile(.qsf)formattotheSynopsysDesignConstraintsFileformat.

--sdc=<SDCfile>

Specifiesthe.sdcfiletoread.

--fast_model

Usesthefastcornerdelaymodels.

--report_script=<script>

Specifiesacustomreportscripttobecalled.

--speed=<value>

Specifiesthedevicespeedgradetobeusedfortiming ysis.

--tq2hc

GeneratetemporaryfilestoconverttheQuartusIITimeQuestTimingyzer.sdcfile(s)toaPrimeTime.sdcfilethatcanbeusedbytheDesignCenter(HCDC).

--tq2pt

GeneratestemporaryfilestoconverttheQuartusIITimeQuestTiming yzer.sdc

file(s)toaPrimeTime.sdcfile.

-f<argumentfile>

Specifiesafilecontainingadditionalcommand-linearguments.

-c<revisionname>|

--rev=<revision_name>

SpecifieswhichrevisionanditsassociatedQuartusIISettingsFile(.qsf)touse.

--multicorner

Specifiesthatallslacksummaryreportsbegeneratedforbothslowandfastcorners.

ToruntheQuartusIITimeQuestTiming yzerincommand-linemode,typethefollowingcommandatthecommandprompt:

quartus_sta<options>r

Timing ysisOverview

ThissectionprovidesanoverviewoftheQuartusIITimeQuestTimingyzerconcepts.Understandingtheseconceptsallowsyoutotakeadvantageofthepowerfultiming ysisfeaturesavailableintheQuartusIITimeQuestTimingyzer.

TheQuartusIITimeQuestTiming yzerfollowstheflowshowninFigure7–2whenit yzesyourdesign.Table7–2liststhemostcommonlyusedcommandsforeachstep.

create_generated_clockderive_pll_clocksset_input_delayset_output_delay

...

set_clock_uncertaintyset_clock_latency

ConstraintheDesign

create_clock

VerifyStaticTiming ysisResults

report_clocks_transfersreport_min_pulse_width

report_net_timing

report_sdcreport_timingreport_clocks

report_min_pulse_widthreport_ucp

UpdateTimingNetlist

update_timing_netlist

CreateTimingNetlist

create_timing_netlist

OpenProject

project_open

Figure7–2.TheQuartusIITimeQuestTimingyzerFlow

Table7–2describesQuartusIITimeQuestTimingyzerterminology.

Table7–2.QuartusIITimeQuestTiming yzerTerms

Terminology

Definition

Nodes

Mostbasictimingnetlistunit.Usetorepresentports,pins,andregisters.

Keepers

Portsorregisters.(1)

Cells

Look-uptable(LUT),registers,digitalsignalprocessing(DSP)blocks,TriMatrixmemory,IOE,andsoon.(2)

Pins

Inputsoroutputsofcells.

Nets

Connectionsbetweenpins.

Ports

Top-levelmoduleinputsoroutputs;forexample,devicepins.

Clocks

objectsoutsideofthedesign.

NotestoTable7–2:

Pinscanindirectlyrefertokeepers.Forexample,whenthevalueinthe-fromfieldofaconstraintisaclockpintoadedicatedmemory.Inthiscase,theclockpinreferstoacollectionofregisters.

ForStratix®devicesandotherearlydevicefamilies,theLUTandregistersarecontainedinlogicelements(LE)andacellsforthesedevicefamilies.

TheQuartusIITimeQuestTiming yzerrequiresatimingnetlistbeforeitcanperformatimingysisonanydesign.Forexample,forthedesignshowninFigure7–3,theQuartusIITimeQuestTiming yzergeneratesanetlistequivalenttotheoneshowninFigure7–4.

Figure7–3.SampleDesign

and_inst

reg2

reg1

reg3

data1

data2clk

Cells

Cell

data1

combout

datain

reg1

clk

regout Cell

and_inst

d

data2

Pin

datain

reg2

datad

regout

Port

Pin

clk

clk~clkctrl

inclk0

outclk

Figure7–4.TheQuartusIITimeQuestTiming yzerTimingNetlist

Figure7–4showsvariouscells,pins,nets,andports.Thefollowingsamplecellnamesareincluded:

reg1

reg2

and_inst

Thefollowingsamplepinsnamesareincluded:

data1|combout

reg1|regout

and_inst|combout

Thefollowingnetnamesareincluded:

bout

reg1

and_inst

Thefollowingportnamesareincluded:

data1,clk

data_out

Pathsconnecttwodesignnodes,suchastheoutputofaregistertotheinputofanotherregister.Timingpathsyasignificantroleintiming ysis.

Understandingthetypesoftimingpathsisimportanttotimingclosureandoptimization.Thefollowinglistshowssomeofthecommonlyyzedpathsthataredescribedinthissection:

Edgepaths—theconnectionsfromports-to-pins,frompins-to-pins,andfrompins-to-ports.

Clockpaths—theedgesfromdeviceportsorinternallygeneratedclockpinstotheclockpinofaregister.

Datapaths—theedgesfromaportorthedataoutputpinofasequentialelementtoaportorthedatainputpinofanothersequentialelement.

Asynchronouspaths—theedgesfromaportorsequentialelementtotheasynchronoussetorclearpinofasequentialelement.

Figure7–5showssomeofthesecommonly yzedpathtypes.

Figure7–5.PathTypes

clk

ClockPath

D Q

CLRN

DataPath

D Q

CLRN

AsynchronousClearPath

rst

AftertheQuartusIITimeQuestTiming yzeridentifiesthepathtype,itcanreportdataandclockarrivaltimesforvalidregister-to-registerpaths.TheQuartusIITimeQuestTiming yzercalculatesdataarrivaltimebyaddingthedelayfromtheclocksourcetotheclockpinofthesourceregister,themicroclock-to-out(tCO)ofthesourceregister,andthedelayfromthesourceregister’sQpintothedestinationregister’sDpin,wherethetCOistheintrinsicclock-to-outfortheinternalregistersintheFPGA.

TheQuartusIITimeQuestTiming yzercalculatesclockarrivaltimebyaddingthedelayfromtheclocksourcetothedestinationregister’sclockpin.Figure7–6showsadataarrivalpathandaclockarrivalpath.TheQuartusIITimeQuestTiming

yzercalculatesdatarequiredtimebyaccountingfortheclockarrivaltimeandmicrosetuptime(tSU)ofthedestinationregister,wherethetSUistheintrinsicsetupfortheinternalregistersintheFPGA.

DataArrival

D Q

D Q

Figure7–6.DataArrivalandClockArrival

ClockArrival

Inadditiontoidentifyingvariouspathsinadesign,theQuartusIITimeQuestTimingyzer yzesclockcharacteristicstocomputetheworst-caserequirement

betweenanytworegistersinasingleregister-to-registerpath.Youshouldconstrainallclocksinyourdesignbeforeperformingthis ysis.

Thelaunchedgeisanactiveclockedgetha dsdataoutofasequentialelement,actingasasourceforthedatatransfer.Alatchedgeistheactiveclockedgethatcapturesdataatthedataportofasequentialelement,actingasadestinationforthedatatransfer.

Figure7–7showsasingle-cyclesystemthatusesconsecutiveclockedgestotransferandcapturedata,aregister-to-registerpath,andthecorrespondinglaunchandlatchedgestimingdiagram.Inthiample,thelaunchedgesendsthedataoutofregisterreg1at0ns,andregisterreg2latchedgecapturesthedataat5ns.

D Q

D Q

Figure7–7.LaunchEdgeandLatchEdge

reg2

clk

reg1

0ns

5ns

10ns

15ns

LaunchEdgeat

SourceRegisterreg1

LatchEdgeat

DestinationRegisterreg2

TheQuartusIITimeQuestTiming yzervalidatesclocksetupandholdrequirementsrelativetothelaunchandlatchedges.

Clock ysis

Acomprehensivestatictiming ysisincludes ysisofregister-to-register,I/O,andasynchronousresetpaths.TheQuartusIITimeQuestTimingyzerusesdatarequiredtimes,dataarrivaltimes,andclockarrivaltimestoverifycircuitperformanceanddetectpossibletimingviolations.TheQuartusIITimeQuestTiming

yzerdeterminesthetimingrelationshipsthatmustbemetforthedesigntocorrectlyfunctionandchecksarrivaltimesagainstrequiredtimestoverifytiming.

ClockSetupCheck

Toperformaclocksetupcheck,theQuartusIITimeQuestTiming yzerdeterminesasetuprelationshipby yzingeachlaunchandlatchedgeforeachregister-to-registerpath.Foreachlatchedgeatthedestinationregister,theQuartusIITimeQuestTiming yzerusestheclosestpreviousclockedgeatthesourceregisterasthelaunchedge.InFigure7–8,twosetuprelationshipsaredefinedandarelabeledsetupAandsetupB.Forthelatchedgeat10ns,theclosestclockthtsasalaunchedgeisat3nsandislabeledsetupA.Forthelatchedgeat20ns,theclosestclockthatactsasalaunchedgeis19nsandislabeledsetupB.

Figure7–8.SetupCheck

SetupA

SetupB

SourceClock

DestinationClock

0ns 8ns 16ns 24ns 32ns

TheQuartusIITimeQuestTiming yzerreportstheresultofclocksetupchecksasslackvalues.Slackisthemarginbywhichatimingrequirementismetornotmet.

Positiveslackindicatesthemarginbywhicharequirementismet;negativeslackindicatesthemarginbywhicharequirementisnotmet.TheQuartusIITimeQuestTiming yzerdeterminesclocksetupslack,asshowninEquation7–1,forinternalregister-to-registerpaths.

Equation7–1.

ClockSetupSlack=DataRequiredTime–DataArrivalTime

DataArrivalTime=LaunchEdge+ClockNetworkDelaytoSourceRegister+

tCO+Register-to-RegisterDelay

DataRequired=ClockArrivalTime–tSU–SetupUncertainty

ClockArrivalTime=LatchEdge+ClockNetworkDelaytoDestinationRegister

Ifthedatapathisfromaninputporttoainternalregister,theQuartusIITimeQuestTiming yzerusestheequationsshowninEquation7–2tocalculatethesetupslacktime.

Equation7–2.

ClockSetupSlackTime=DataRequiredTime–DataArrivalTimeDataArrivalTime=LaunchEdge+ClockNetworkDelay+

Input umDelayofPin+Pin-to-RegisterDelay

DataRequiredTime=LatchEdge+ClockNetworkDelaytoDestinationRegister–tSU

Ifthedatapathisaninternalregistertoanoutputport,theQuartusIITimeQuestTimingyzerusestheequationsshowninEquation7–3tocalculatethesetupslacktime.

Equation7–3.

ClockSetupSlackTime=DataRequiredTime–DataArrivalTime

DataArrivalTime=LaunchEdge+ClockNetworkDelaytoSourceRegister+

tCO+Register-to-PinDelay

DataRequiredTime=LatchEdge+ClockNetworkDelay–Output umDelayofPin

ClockHoldCheck

Toperformaclockholdcheck,theQuartusIITimeQuestTiming yzerdeterminesaholdrelationshipforeachpossiblesetuprelationshipthatexistsforallsourceanddestinationregisterpairs.TheQuartusIITimeQuestTiming yzerchecksalladjacentclockedgesfromallsetuprelationshipstodeterminetheholdrelationships.TheQuartusIITimeQuestTiming yzerperformstwoholdchecksforeachsetuprelationship.Thefirstholdcheckdeterminesthatthedatalaunchedbythecurrentlaunchedgeisnotcapturedbythepreviouslatchedge.Thesecondholdcheckdeterminesthatthedatalaunchedbythenextlaunchedgeisnotcapturedbythecurrentlatchedge.Figure7–9showstwosetuprelationshipslabeledsetupAandsetupB.ThefirstholdcheckislabeledholdcheckA1andholdcheckB1forsetupAandsetupB,respectively.ThesecondholdcheckislabeledholdcheckA2andholdcheckB2forsetupAandsetupB,respectively.

Figure7–9.HoldChecks

k

HoldCheckA1

SetupA

Hold SetupB

CheckA2CheckB1

Hold

HoldCheckB2

k

SourceCloc

DestinationCloc

0ns 8ns 16ns 24ns 32ns

Fromthepossibleholdrelationships,theQuartusIITimeQuestTiming yzerselectstheholdrelationshipthatisthemostrestrictive.Theholdrelationshipwiththelargestdifferencebetweenthelatchandlaunchedges(thatis,latch–launchandnottheabsolutevalueoflatchandlaunch)isselectedbecausethisdeterminestheminimumallowabledelayfortheregister-to-registerpath.ForFigure7–9,theholdrelationshipselectedisholdcheckA2.

TheQuartusIITimeQuestTiming yzerdeterminesclockholdslackasshowninEquation7–4.

Equation7–4.

ClockHoldSlack=DataArrivalTime–DataRequiredTime

DataArrivalTime=LaunchEdge+ClockNetworkDelaytoSourceRegister+tCO+

Register-to-RegisterDelay

DataRequiredTime=ClockArrivalTime+tH+HoldUncertainty

ClockArrivalTime=LatchEdge+ClockNetworkDelaytoDestinationRegister

Ifthedatapathisfromaninputporttoaninternalregister,theQuartusIITimeQuestTimingyzerusestheequationsshowninEquation7–5tocalculatetheholdslacktime.

Equation7–5.

ClockHoldSlackTime=DataArrivalTime–DataRequiredTime

DataArrivalTime=LaunchEdge+ClockNetworkDelay+

InputMinimumDelayofPin+Pin-to-RegisterDelay

DataRequiredTime=LatchEdge+ClockNetworkDelaytoDestinationRegister+tH

Ifthedatapathisaninternalregistertoanoutputport,theQuartusIITimeQuestTiming yzerusestheequationsshowninEquation7–6tocalculatethesetupholdtime.

Equation7–6.

ClockHoldSlackTime=DataArrivalTime–DataRequiredTime

DataArrivalTime=LatchEdge+ClockNetworkDelaytoSourceRegister+tCO+

Register-to-PinDelay

DataRequiredTime=LatchEdge+ClockNetworkDelay–OutputMinimumDelayofPin

RecoveryandRemoval

Recoverytimeistheminimumlengthoftimethede-assertionofanasynchronouscontrolsignal;forexample,clearandpreset,mustbestablebeforethenextactiveclockedge.Therecoveryslacktimecalculationissimilartotheclocksetupslacktimecalculation,butitappliestoasynchronouscontrolsignals.Iftheasynchronouscontrolsignalisregistered,theQuartusIITimeQuestTimingyzerusesEquation7–7tocalculatetherecoveryslacktime.

Equation7–7.

RecoverySlackTime

=DataRequiredTime–DataArrivalTime

DataArrivalTime=LaunchEdge+ClockNetworkDelaytoSourceRegister+

tCO+Register-to-RegisterDelay

DataRequiredTime=LatchEdge+ClockNetworkDelaytoDestinationRegister–tSU

Iftheasynchronouscontrolisnotregistered,theQuartusIITimeQuestTimingyzerusestheequationsshowninEquation7–8tocalculatetherecoveryslack

time.

Equation7–8.

RecoverySlackTime

=DataRequiredTime–DataArrivalTime

DataArrivalTime=LaunchEdge+ClockNetworkDelay+

Port-to-RegisterDelay

umInputDelay+

DataRequiredTime=LatchEdge+ClockNetworkDelaytoDestinationRegisterDelay–tSU

1 Iftheasynchronousresetsignalisfromaport(deviceI/O),youmustmakeanInputumDelayassignmenttotheasynchronousresetportfortheQuartusII

TimeQuestTimingyzertoperformrecovery ysisonthatpath.

Removaltimeistheminimumlengthoftimethede-assertionofanasynchronouscontrolsignalmustbestableaftertheactiveclockedge.TheQuartusIITimeQuestTiming yzerremovaltimeslackcalculationissimilartotheclockholdslackcalculation,butitappliesasynchronouscontrolsignals.Iftheasynchronouscontrolisregistered,theQuartusIITimeQuestTiming yzerusestheequationsshowninEquation7–9tocalculatetheremovalslacktime.

Equation7–9.

RemovalSlackTime=DataArrivalTime–DataRequiredTime

DataArrivalTime=LaunchEdge+ClockNetworkDelaytoSourceRegister+

tCOofSourceRegister+Register-to-RegisterDelay

DataRequiredTime=LatchEdge+ClockNetworkDelaytoDestinationRegister+tH

Iftheasynchronouscontrolisnotregistered,theQuartusIITimeQuestTimingyzerusestheequationsshowninEquation7–10tocalculatetheremovalslack

time.

Equation7–10.

RemovalSlackTime=DataArrivalTime–DataRequiredTime

DataArrivalTime=LaunchEdge+ClockNetworkDelay+InputMinimumDelayofPin+

MinimumPin-to-RegisterDelay

DataRequiredTime=LatchEdge+ClockNetworkDelaytoDestinationRegister+tH

1 Iftheasynchronousresetsignalisfromadevicepin,youmustspecifytheInputMinimumDelayconstrainttotheasynchronousresetpinfortheQuartusIITimeQuestTimingyzertoperformaremoval ysisonthispath.

MulticyclePaths

Multicyclepathsaredatapathsthatrequiremorethanoneclockcycletolatchdataatthedestinationregister.Forexample,aregistermayberequiredtocapturedataoneverysecondorthirdrisingclockedge.Figure7–10showsanexampleofamulticyclepathbetweenamultiplier’sinputregistersandoutputregisterwherethedestinationlatchesdataoneveryotherclockedge.

2Cycles

D Q

ENA

D Q

ENA

D Q

ENA

D Q

Figure7–10.ExampleDiagramofaMulticyclePath

Figure7–11showsaregister-to-registerpathwherethesourceclock,src_clk,hasaperiodof10nsandthedestinationclock,dst_clk,hasaperiodof5ns.

Figure7–11.Register-to-RegisterPath

data_in

src_clk

dst_clk

reg reg

D Q

D Q

data_out

Figure7–12showstherespectivetimingdiagramsforthesourceanddestinationclocksandthedefaultsetupandholdrelationships.Thedefaultsetuprelationshipis5ns;thedefaultholdrelationshipis0ns.

Figure7–12.DefaultSetupandHoldTimingDiagram

setuphold

0 10 20 30

Thedefaultsetupandholdrelationshipscanbemodifiedwiththe

set_multicycle_pathcommandto modatethesystemrequirements.

Table7–3showsthecommandsusedtomodifyeitherthelaunchorlatchedgetimesthattheQuartusIITimeQuestTiming yzerTiming yzerusestodetermineasetuprelationshiporholdrelationship.

Table7–3.CommandstoModifyEdgeTimes

Command

DescriptionofModification

set_multicycle_path-setup-end

Latchedgetimeofthesetuprelationship

set_multicycle_path-setup-start

Launchedgetimeofthesetuprelationship

set_multicycle_path-hold-end

Latchedgetimeoftheholdrelationship

set_multicycle_path-hold-start

Launchedgetimeoftheholdrelationship

Figure7–13showsthetimingdiagramaf multicyclesetupoftwohasbeenapplied.Thecommandmovesthelatchedgetimeto10nsfromthedefault