EDA技术及应用实验报告四

EDA技术及应用实验报告1/12

EDA技术及应用实验报告实验四数字频率计的设计 学生姓名张志翔班级电子信息工程1203班学号12401720522指导教师2015.4.28实验四数字频率计的设计一、实验目的1.掌握VHDL语言的基本结构。2.掌握VHDL层次化的设计方法。3.掌握VHDL基本逻辑电路的综合设计应用。二、实验内容设计并调试好一个8位十进制数字频率计。要求编写上述8位十进制数字频率计逻辑图中的各个模块的VHDL语言程序，并完成8位十进制数字频率计的顶层设计，然后利用开发工具软件对其进行编译和仿真，最后通过实验开发系统对其进行硬件验证。三、实验条件1.计算机一台；2.Max+PlusII和QuartusII开发工具软件；3.EDA实验开发箱一台；4.编程器件：EP3C55U48417四、实验步骤1.根据测频控制信号发生器的基本原理编写TESTCTL模块的VHDL程序，并对其进行编译和仿真，初步验证设计的正确性。2.编写十进制计数器CNT10模块的VHDL程序，并对其进行编译和仿真，初步验证设计的正确性。3.编写寄存器REG32B模块的VHDL程序，并对其进行编译和仿真，初步验证设计的正确性。4.完成8位十进制数字频率计的顶层设计，并对其进行编译和仿真，初步验证设计的正确性。5.利用开发工具软件，选择所用可编程逻辑器件，并对8位十进制数字频率计进行管脚配置。6.通过下载电缆将编译后的*.pof文件下载到目标器件之中，并利用实验开发装置对其进行硬件验证。五、实验原理1.系统设计思路图1是8位十进制数字频率计的电路逻辑图，它由一个测频控制信号发生器TESTCTL、8个有时钟使能的十进制计数器CNT10、一个32位锁存器REG32B组成。以下分别叙述频率计各逻辑模块的功能与设计方法。2.VHDL源程序1)十进制计数器的源程序CNT10.VHD--CNT10.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYCNT10IS PORT(CLK,CLR,ENA:INSTD_LOGIC; CQ:OUTINTEGERRANGE0TO15; CO:OUTSTD_LOGIC);ENDENTITYCNT10;ARCHITECTUREARTOFCNT10IS SIGNALCQI:INTEGERRANGE0TO15; BEGIN PROCESS(CLK,CLR,ENA)IS BEGIN IFCLR='1'THENCQI<=0; ELSIFCLK'EVENTANDCLK='1'THEN IFENA='1'THEN IFCQI<9THEN CQI<=CQI+1; ELSE CQI<=0; ENDIF; ENDIF; ENDIF; ENDPROCESS; PROCESS(CQI)IS BEGIN IFCQI=9THENCO<='1'; ELSE CO<='0'; ENDIF; ENDPROCESS; CQ<=CQI;ENDARCHITECTUREART;2）32位锁存器源程序REG32B.VHD--REG32B.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYREG32BISPORT(LOAD:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(31DOWNTO0);DOUT:OUTSTD_LOGIC_VECTOR(31DOWNTO0));ENDREG32B;ARCHITECTUREARTOFREG32BISBEGINPROCESS(LOAD,DIN)ISBEGINIFLOAD'EVENTANDLOAD='1'THENDOUT<=DIN;ENDIF;ENDPROCESS;ENDARCHITECTUREART;3)信号发生器源程序TESTCL.VHD--TESTCTL.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYTESTCTLIS PORT(CLK:INSTD_LOGIC; TSTEN:OUTSTD_LOGIC; CLR_CNT:OUTSTD_LOGIC; LOAD:OUTSTD_LOGIC);ENDENTITYTESTCTL;ARCHITECTUREARTOFTESTCTLIS SIGNALDIV2CLK:STD_LOGIC; BEGIN PROCESS(CLK)IS BEGIN IFCLK'EVENTANDCLK='1'THEN DIV2CLK<=NOTDIV2CLK; ENDIF; ENDPROCESS; PROCESS(CLK,DIV2CLK)IS BEGIN IFCLK='0'ANDDIV2CLK='0'THEN CLR_CNT<='1'; ELSECLR_CNT<='0'; ENDIF; ENDPROCESS; LOAD<=NOTDIV2CLK; TSTEN<=DIV2CLK;ENDARCHITECTUREART;4）CTRLS.VHD--CTRLS.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCTRLSIS PORT(CLK:INSTD_LOGIC; SEL:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDENTITYCTRLS;ARCHITECTUREARTOFCTRLSIS SIGNALCNT:STD_LOGIC_VECTOR(2DOWNTO0); BEGIN PROCESS(CLK)IS BEGIN IFCLK'EVENTANDCLK='1'THEN IFCNT="111"THEN CNT<="000"; ELSE CNT<=CNT+'1'; ENDIF; ENDIF; ENDPROCESS; SEL<=CNT;ENDARCHITECTUREART;5）DISPLAY.VHD--DISPLAY.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYDISPLAYIS PORT(SEL:INSTD_LOGIC_VECTOR(2DOWNTO0); DATAIN:INSTD_LOGIC_VECTOR(31DOWNTO0); COM:OUTSTD_LOGIC_VECTOR(7DOWNTO0); --LEDW:OUTSTD_LOGIC_VECTOR(2DOWNTO0); SEG:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYDISPLAY;ARCHITECTUREARTOFDISPLAYIS SIGNALDATA:STD_LOGIC_VECTOR(3DOWNTO0); BEGIN P1:PROCESS(SEL)IS BEGIN CASESELIS WHEN"000"=>COM<="11111110"; WHEN"001"=>COM<="11111101"; WHEN"010"=>COM<="11111011"; WHEN"011"=>COM<="11110111"; WHEN"100"=>COM<="11101111"; WHEN"101"=>COM<="11011111"; WHEN"110"=>COM<="10111111"; WHEN"111"=>COM<="01111111"; WHENOTHERS=>COM<="11111111"; ENDCASE; ENDPROCESSP1; --LEDW<=SEL; P2:PROCESS(SEL) BEGIN CASESELIS WHEN"000"=>DATA<=DATAIN(3DOWNTO0); WHEN"001"=>DATA<=DATAIN(7DOWNTO4); WHEN"010"=>DATA<=DATAIN(11DOWNTO8); WHEN"011"=>DATA<=DATAIN(15DOWNTO12); WHEN"100"=>DATA<=DATAIN(19DOWNTO16); WHEN"101"=>DATA<=DATAIN(23DOWNTO20); WHEN"110"=>DATA<=DATAIN(27DOWNTO24); WHEN"111"=>DATA<=DATAIN(31DOWNTO28); WHENOTHERS=>DATA<="0000"; ENDCASE; CASEDATAIS WHEN"0000"=>SEG<="00111111"; --3FH WHEN"0001"=>SEG<="00000110"; --06H WHEN"0010"=>SEG<="01011011"; --5BH WHEN"0011"=>SEG<="01001111"; --4FH WHEN"0100"=>SEG<="01100110"; --66H WHEN"0101"=>SEG<="01101101"; --6DH WHEN"0110"=>SEG<="01111101"; --7DH WHEN"0111"=>SEG<="00000111"; --07H WHEN"1000"=>SEG<="01111111"; --7FH WHEN"1001"=>SEG<="01101111"; --6FH WHENOTHERS=>SEG<="00000000"; --00H ENDCASE; ENDPROCESSP2;ENDARCHITECTUREART; 6）CLKGEN.VHD--CLKGEN.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCLKGENIS PORT(CLK_IN:INSTD_LOGIC; RESET:INSTD_LOGIC; CLK_OUT:OUTSTD_LOGIC);ENDENTITYCLKGEN;ARCHITECTUREARTOFCLKGENIS CONSTANTDIVIDE_PERIOD:INTEGER:=500000; --CONSTANTDIVIDE_PERIOD:INTEGER:=20; BEGIN PROCESS(CLK_IN,RESET)IS VARIABLECNT:INTEGERRANGE0TO499999; --VARIABLECNT:INTEGERRANGE0TO19; BEGIN IF(RESET='1')THEN CNT:=0; CLK_OUT<='0'; ELSIFRISING_EDGE(CLK_IN)THEN IF(CNT<(DIVIDE_PERIOD/2))THEN CLK_OUT<='1'; CNT:=CNT+1; ELSIF(CNT<(DIVIDE_PERIOD-1))THEN CLK_OUT<='0'; CNT:=CNT+1; ELSE CNT:=0; ENDIF; ENDIF; ENDPROCESSDIVIDE_CLK;ENDARCHITECTUREART;7)FREQ.VHD--FREQ.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYFREQISPORT(FSIN:INSTD_LOGIC;--5ns\10ns\5nsCLK:INSTD_LOGIC;--500nsCLK2:INSTD_LOGIC;RESET:INSTD_LOGIC;SEG:OUTSTD_LOGIC_VECTOR(7DOWNTO0);COM:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYFREQ;ARCHITECTUREARTOFFREQIS--CNT10COMPONENTCNT10ISPORT(CLK,CLR,ENA:INSTD_LOGIC;CQ:OUTSTD_LOGIC_VECTOR(3DOWNTO0);CO:OUTSTD_LOGIC);ENDCOMPONENTCNT10;--REG32BCOMPONENTREG32BISPORT(LOAD:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(31DOWNTO0);DOUT:OUTSTD_LOGIC_VECTOR(31DOWNTO0));ENDCOMPONENTREG32B;--TESTCTLCOMPONENTTESTCTLISPORT(CLK:INSTD_LOGIC;TSTEN:OUTSTD_LOGIC;CLR_CNT:OUTSTD_LOGIC;LOAD:OUTSTD_LOGIC);ENDCOMPONENTTESTCTL;--CLKGENCOMPONENTCLKGENISPORT(CLK_IN:INSTD_LOGIC;RESET:INSTD_LOGIC;CLK_OUT:OUTSTD_LOGIC);ENDCOMPONENTCLKGEN;--CTRLSCOMPONENTCTRLSISPORT(CLK:INSTD_LOGIC;SEL:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDCOMPONENTCTRLS;--DISPLAYCOMPONENTDISPLAYISPORT(SEL:INSTD_LOGIC_VECTOR(2DOWNTO0);DATAIN:INSTD_LOGIC_VECTOR(31DOWNTO0);COM:OUTSTD_LOGIC_VECTOR(7DOWNTO0);SEG:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENTDISPLAY;SIGNALSE,SC,SL,CLK1:STD_LOGIC;SIGNALS0,S1,S2,S3,S4,S5,S6,S7,S8:STD_LOGIC;SIGNALSD,DOUT:STD_LOGIC_VECTOR(31DOWNTO0);SIGNALSEL:STD_LOGIC_VECTOR(2DOWNTO0);BEGINU0:CLKGENPORTMAP(CLK,RESET,CLK1);U1:TESTCTLPORTMAP(CLK=>CLK1,TSTEN=>SE,CLR_CNT=>SC,LOAD=>SL);U2:CNT10PORTMAP(CLK=>FSIN,CLR=>SC,ENA=>SE,CQ=>SD(3DOWNTO0),CO=>S1);U3:CNT10PORT