LM3S5P51IBZ80C3T系列规格书,Datasheet资料综合文库

1/1LM3S5P51-IBZ80-C3T系列规格书,Datasheet资料-综合文库

Stellaris?

LM3S5P51Microcontroller

DATASHEETCopyright?2022-2023

TexasInstrumentsIncorporated

DS-LM3S5P51-11425TEXASINSTRUMENTS-PRODUCTIONDATA

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Copyright

Copyright?2022-2023TexasInstrumentsIncorporatedAllrightsreserved.StellarisandStellarisWare?areregisteredtrademarksofTexasInstrumentsIncorporated.ARMandThumbareregisteredtrademarksandCortexisatrademarkofARMLimited.Othernamesandbrandsmaybeclaimedasthepropertyofothers.

PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsofTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.

Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.

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Stellaris?LM3S5P51Microcontroller

TableofContents

RevisionHistory(37)

AboutThisDocument(46)

Audience(46)

AboutThisManual(46)

RelatedDocuments(46)

DocumentationConventions(47)

1ArchitecturalOverview(49)

1.1Overview(49)

1.2TargetApplications(51)

1.3Features(51)

1.3.1ARMCortex-M3ProcessorCore(51)

1.3.2On-ChipMemory(53)

1.3.3SerialCommunicationsPeripherals(54)

1.3.4SystemIntegration(59)

1.3.5AdvancedMotionControl(65)

1.3.6Analog(67)

1.3.7JTAGandARMSerialWireDebug(68)

1.3.8PackagingandTemperature(69)

1.4HardwareDetails(69)

2TheCortex-M3Processor(70)

2.1BlockDiagram(71)

2.2Overview(72)

2.2.1System-LevelInterface(72)

2.2.2IntegratedConfigurableDebug(72)

2.2.3TracePortInterfaceUnit(TPIU)(73)

2.2.4Cortex-M3SystemComponentDetails(73)

2.3ProgrammingModel(74)

2.3.1ProcessorModeandPrivilegeLevelsforSoftwareExecution(74)

2.3.2Stacks(74)

2.3.3RegisterMap(75)

2.3.4RegisterDescriptions(76)

2.3.5ExceptionsandInterrupts(89)

2.3.6DataTypes(89)

2.4MemoryModel(89)

2.4.1MemoryRegions,TypesandAttributes(91)

2.4.2MemorySystemOrderingofMemoryAccesses(92)

2.4.3BehaviorofMemoryAccesses(92)

2.4.4SoftwareOrderingofMemoryAccesses(92)

2.4.5Bit-Banding(94)

2.4.6DataStorage(96)

2.4.7SynchronizationPrimitives(97)

2.5ExceptionModel(98)

2.5.1ExceptionStates(99)

2.5.2ExceptionTypes(99)

2.5.3ExceptionHandlers(102)

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2.5.4VectorTable(102)

2.5.5ExceptionPriorities(103)

2.5.6InterruptPriorityGrouping(104)

2.5.7ExceptionEntryandReturn(104)

2.6FaultHandling(106)

2.6.1FaultTypes(106)

2.6.2FaultEscalationandHardFaults(107)

2.6.3FaultStatusRegistersandFaultAddressRegisters(108)

2.6.4Lockup(108)

2.7PowerManagement(108)

2.7.1EnteringSleepModes(108)

2.7.2WakeUpfromSleepMode(109)

2.8InstructionSetSummary(110)

3Cortex-M3Peripherals(113)

3.1FunctionalDescription(113)

3.1.1SystemTimer(SysTick)(113)

3.1.2NestedVectoredInterruptController(NVIC)(114)

3.1.3SystemControlBlock(SCB)(116)

3.1.4MemoryProtectionUnit(MPU)(116)

3.2RegisterMap(121)

3.3SystemTimer(SysTick)RegisterDescriptions(123)

3.4NVICRegisterDescriptions(127)

3.5SystemControlBlock(SCB)RegisterDescriptions(140)

3.6MemoryProtectionUnit(MPU)RegisterDescriptions(169)

4JTAGInterface(179)

4.1BlockDiagram(180)

4.2SignalDescription(180)

4.3FunctionalDescription(181)

4.3.1JTAGInterfacePins(181)

4.3.2JTAGTAPController(183)

4.3.3ShiftRegisters(183)

4.3.4OperationalConsiderations(184)

4.4InitializationandConfiguration(186)

4.5RegisterDescriptions(187)

4.5.1InstructionRegister(IR)(187)

4.5.2DataRegisters(189)

5SystemControl(191)

5.1SignalDescription(191)

5.2FunctionalDescription(191)

5.2.1DeviceIdentification(192)

5.2.2ResetControl(192)

5.2.3Non-MaskableInterrupt(197)

5.2.4PowerControl(197)

5.2.5ClockControl(198)

5.2.6SystemControl(206)

5.3InitializationandConfiguration(207)

5.4RegisterMap(208)

5.5RegisterDescriptions(209)

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Stellaris?LM3S5P51Microcontroller6HibernationModule(295)

6.1BlockDiagram(296)

6.2SignalDescription(296)

6.3FunctionalDescription(297)

6.3.1RegisterAccessTiming(297)

6.3.2HibernationClockSource(298)

6.3.3SystemImplementation(299)

6.3.4BatteryManagement(300)

6.3.5Real-TimeClock(300)

6.3.6Battery-BackedMemory(301)

6.3.7PowerControlUsingHIB(301)

6.3.8PowerControlUsingVDD3ONMode(301)

6.3.9InitiatingHibernate(301)

6.3.10WakingfromHibernate(301)

6.3.11InterruptsandStatus(302)

6.4InitializationandConfiguration(302)

6.4.1Initialization(302)

6.4.2RTCMatchFunctionality(NoHibernation)(303)

6.4.3RTCMatch/Wake-UpfromHibernation(303)

6.4.4ExternalWake-UpfromHibernation(304)

6.4.5RTCorExternalWake-UpfromHibernation(304)

6.5RegisterMap(304)

6.6RegisterDescriptions(305)

7InternalMemory(322)

7.1BlockDiagram(322)

7.2FunctionalDescription(322)

7.2.1SRAM(323)

7.2.2ROM(323)

7.2.3FlashMemory(325)

7.3RegisterMap(330)

7.4FlashMemoryRegisterDescriptions(FlashControlOffset)(331)

7.5MemoryRegisterDescriptions(SystemControlOffset)(343)

8MicroDirectMemoryAccess(μDMA)(359)

8.1BlockDiagram(360)

8.2FunctionalDescription(360)

8.2.1ChannelAssignments(361)

8.2.2Priority(362)

8.2.3ArbitrationSize(362)

8.2.4RequestTypes(362)

8.2.5ChannelConfiguration(363)

8.2.6TransferModes(365)

8.2.7TransferSizeandIncrement(373)

8.2.8PeripheralInterface(373)

8.2.9SoftwareRequest(373)

8.2.10InterruptsandErrors(374)

8.3InitializationandConfiguration(374)

8.3.1ModuleInitialization(374)

8.3.2ConfiguringaMemory-to-MemoryTransfer(374)

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8.3.3ConfiguringaPeripheralforSimpleTransmit(376)

8.3.4ConfiguringaPeripheralforPing-PongReceive(377)

8.3.5ConfiguringChannelAssignments(380)

8.4RegisterMap(380)

8.5μDMAChannelControlStructure(381)

8.6μDMARegisterDescriptions(388)

9General-PurposeInput/Outputs(GPIOs)(417)

9.1SignalDescription(417)

9.2FunctionalDescription(422)

9.2.1DataControl(423)

9.2.2InterruptControl(424)

9.2.3ModeControl(425)

9.2.4CommitControl(425)

9.2.5PadControl(426)

9.2.6Identification(426)

9.3InitializationandConfiguration(426)

9.4RegisterMap(427)

9.5RegisterDescriptions(430)

10General-PurposeTimers(473)

10.1BlockDiagram(474)

10.2SignalDescription(474)

10.3FunctionalDescription(477)

10.3.1GPTMResetConditions(478)

10.3.2TimerModes(478)

10.3.3DMAOperation(484)

10.3.4AccessingConcatenatedRegisterValues(485)

10.4InitializationandConfiguration(485)

10.4.1One-Shot/PeriodicTimerMode(485)

10.4.2Real-TimeClock(RTC)Mode(486)

10.4.3InputEdge-CountMode(486)

10.4.4InputEdgeTimingMode(487)

10.4.5PWMMode(488)

10.5RegisterMap(488)

10.6RegisterDescriptions(489)

11WatchdogTimers(520)

11.1BlockDiagram(521)

11.2FunctionalDescription(521)

11.2.1RegisterAccessTiming(522)

11.3InitializationandConfiguration(522)

11.4RegisterMap(522)

11.5RegisterDescriptions(523)

12Analog-to-DigitalConverter(ADC)(545)

12.1BlockDiagram(546)

12.2SignalDescription(547)

12.3FunctionalDescription(549)

12.3.1SampleSequencers(549)

12.3.2ModuleControl(550)

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12.3.3HardwareSampleAveragingCircuit(552)

12.3.4Analog-to-DigitalConverter(553)

12.3.5DifferentialSampling(556)

12.3.6InternalTemperatureSensor(559)

12.3.7DigitalComparatorUnit(559)

12.4InitializationandConfiguration(564)

12.4.1ModuleInitialization(564)

12.4.2SampleSequencerConfiguration(565)

12.5RegisterMap(565)

12.6RegisterDescriptions(567)

13UniversalAsynchronousReceivers/Transmitters(UARTs)(625)

13.1BlockDiagram(626)

13.2SignalDescription(626)

13.3FunctionalDescription(628)

13.3.1Transmit/ReceiveLogic(628)

13.3.2Baud-RateGeneration(629)

13.3.3DataTransmission(630)

13.3.4SerialIR(SIR)(630)

13.3.5ISO7816Support(631)

13.3.6ModemHandshakeSupport(631)

13.3.7LINSupport(633)

13.3.8FIFOOperation(634)

13.3.9Interrupts(635)

13.3.10LoopbackOperation(636)

13.3.11DMAOperation(636)

13.4InitializationandConfiguration(636)

13.5RegisterMap(637)

13.6RegisterDescriptions(639)

14SynchronousSerialInterface(SSI)(689)

14.1BlockDiagram(690)

14.2SignalDescription(690)

14.3FunctionalDescription(691)

14.3.1BitRateGeneration(692)

14.3.2FIFOOperation(692)

14.3.3Interrupts(692)

14.3.4FrameFormats(693)

14.3.5DMAOperation(700)

14.4InitializationandConfiguration(701)

14.5RegisterMap(702)

14.6RegisterDescriptions(703)

15Inter-IntegratedCircuit(I2C)Interface(731)

15.1BlockDiagram(732)

15.2SignalDescription(732)

15.3FunctionalDescription(733)

15.3.1I2CBusFunctionalOverview(733)

15.3.2AvailableSpeedModes(735)

15.3.3Interrupts(736)

15.3.4LoopbackOperation(737)

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15.3.5CommandSequenceFlowCharts(738)

15.4InitializationandConfiguration(745)

15.5RegisterMap(746)

15.6RegisterDescriptions(I2CMaster)(747)

15.7RegisterDescriptions(I2CSlave)(760)

16Inter-IntegratedCircuitSound(I2S)Interface(769)

16.1BlockDiagram(770)

16.2SignalDescription(770)

16.3FunctionalDescription(772)

16.3.1Transmit(773)

16.3.2Receive(777)

16.4InitializationandConfiguration(779)

16.5RegisterMap(780)

16.6RegisterDescriptions(781)

17ControllerAreaNetwork(CAN)Module(806)

17.1BlockDiagram(807)

17.2SignalDescription(807)

17.3FunctionalDescription(808)

17.3.1Initialization(809)

17.3.2Operation(810)

17.3.3TransmittingMessageObjects(811)

17.3.4ConfiguringaTransmitMessageObject(811)

17.3.5UpdatingaTransmitMessageObject(812)

17.3.6AcceptingReceivedMessageObjects(813)

17.3.7ReceivingaDataFrame(813)

17.3.8ReceivingaRemoteFrame(813)

17.3.9Receive/TransmitPriority(814)

17.3.10ConfiguringaReceiveMessageObject(814)

17.3.11HandlingofReceivedMessageObjects(815)

17.3.12HandlingofInterrupts(817)

17.3.13TestMode(818)

17.3.14BitTimingConfigurationErrorConsiderations(820)

17.3.15BitTimeandBitRate(820)

17.3.16CalculatingtheBitTimingParameters(822)

17.4RegisterMap(825)

17.5CANRegisterDescriptions(826)

18UniversalSerialBus(USB)Controller(857)

18.1BlockDiagram(858)

18.2SignalDescription(858)

18.3FunctionalDescription(860)

18.3.1OperationasaDevice(860)

18.3.2OperationasaHost(865)

18.3.3OTGMode(869)

18.3.4DMAOperation(871)

18.4InitializationandConfiguration(872)

18.4.1PinConfiguration(872)

18.4.2EndpointConfiguration(872)

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18.5RegisterMap(873)

18.6RegisterDescriptions(884)

19AnalogComparators(996)

19.1BlockDiagram(996)

19.2SignalDescription(997)

19.3FunctionalDescription(998)

19.3.1InternalReferenceProgramming(998)

19.4InitializationandConfiguration(1000)

19.5RegisterMap(1001)

19.6RegisterDescriptions(1001)

20PulseWidthModulator(PWM)(1009)

20.1BlockDiagram(1010)

20.2SignalDescription(1011)

20.3FunctionalDescription(1014)

20.3.1PWMTimer(1014)

20.3.2PWMComparators(1014)

20.3.3PWMSignalGenerator(1016)

20.3.4Dead-BandGenerator(1017)

20.3.5Interrupt/ADC-TriggerSelector(1017)

20.3.6SynchronizationMethods(1017)

20.3.7FaultConditions(1018)

20.3.8OutputControlBlock(1019)

20.4InitializationandConfiguration(1020)

20.5RegisterMap(1020)

20.6RegisterDescriptions(1023)

21QuadratureEncoderInterface(QEI)(1082)

21.1BlockDiagram(1082)

21.2SignalDescription(1083)

21.3FunctionalDescription(1084)

21.4InitializationandConfiguration(1087)

21.5RegisterMap(1087)

21.6RegisterDescriptions(1088)

22PinDiagram(1105)

23SignalTables(1107)

23.1100-PinLQFPPackagePinTables(1108)

23.2108-BallBGAPackagePinTables(1142)

23.3ConnectionsforUnusedSignals(1177)

24OperatingCharacteristics(1179)

25ElectricalCharacteristics(1180)

25.1MaximumRatings(1180)

25.2RecommendedOperatingConditions(1180)

25.3LoadConditions(1181)

25.4JTAGandBoundaryScan(1181)

25.5PowerandBrown-Out(1183)

25.6Reset(1184)

25.7On-ChipLowDrop-Out(LDO)Regulator(1185)

25.8Clocks(1185)

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25.8.1PLLSpecifications(1185)

25.8.2PIOSCSpecifications(1186)

25.8.3Internal30-kHzOscillatorSpecifications(1186)

25.8.4HibernationClockSourceSpecifications(1187)

25.8.5MainOscillatorSpecifications(1187)

25.8.6SystemClockSpecificationwithADCOperation(1188)

25.8.7SystemClockSpecificationwithUSBOperation(1188)

25.9SleepModes(1188)

25.10HibernationModule(1189)

25.11FlashMemory(1190)

25.12Input/OutputCharacteristics(1190)

25.13Analog-to-DigitalConverter(ADC)(1191)

25.14SynchronousSerialInterface(SSI)(1192)

25.15Inter-IntegratedCircuit(I2C)Interface(1194)

25.16Inter-IntegratedCircuitSound(I2S)Interface(1195)

25.17UniversalSerialBus(USB)Controller(1196)

25.18AnalogComparator(1197)

25.19CurrentConsumption(1197)

25.19.1NominalPowerConsumption(1197)

25.19.2MaximumCurrentConsumption(1198)

ARegisterQuickReference(1200)

BOrderingandContactInformation(1249)

B.1OrderingInformation(1249)

B.2PartMarkings(1249)

B.3Kits(1250)

B.4SupportInformation(1250)

CPackageInformation(1251)

C.1100-PinLQFPPackage(1251)

C.1.1PackageDimensions(1251)

C.1.2TrayDimensions(1253)

C.1.3TapeandReelDimensions(1253)

C.2108-BallBGAPackage(1255)

C.2.1PackageDimensions(1255)

C.2.2TrayDimensions(1257)

C.2.3TapeandReelDimensions(1258)

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ListofFigures

Figure1-1.StellarisLM3S5P51MicrocontrollerHigh-LevelBlockDiagram(50)

Figure2-1.CPUBlockDiagram(72)

Figure2-2.TPIUBlockDiagram(73)

Figure2-3.Cortex-M3RegisterSet(75)

Figure2-4.Bit-BandMapping(96)

Figure2-5.DataStorage(97)

Figure2-6.VectorTable(103)

Figure2-7.ExceptionStackFrame(105)

Figure3-1.SRDUseExample(119)

Figure4-1.JTAGModuleBlockDiagram(180)

Figure4-2.TestAccessPortStateMachine(183)

Figure4-3.IDCODERegisterFormat(189)

Figure4-4.BYPASSRegisterFormat(189)

Figure4-5.BoundaryScanRegisterFormat(190)

Figure5-1.BasicRSTConfiguration(194)

Figure5-2.ExternalCircuitrytoExtendPower-OnReset(194)

Figure5-3.ResetCircuitControlledbySwitch(195)

Figure5-4.PowerArchitecture(198)

Figure5-5.MainClockTree(201)

Figure6-1.HibernationModuleBlockDiagram(296)

5dbd71cb7f1922791688e8bdingaCrystalastheHibernationClockSource(299)

5dbd71cb7f1922791688e8bdingaDedicatedOscillatorastheHibernationClockSourcewithVDD3ON

Mode(299)

Figure7-1.InternalMemoryBlockDiagram(322)

Figure8-1.μDMABlockDiagram(360)

Figure8-2.ExampleofPing-PongμDMATransaction(366)

Figure8-3.MemoryScatter-Gather,SetupandConfiguration(368)

Figure8-4.MemoryScatter-Gather,μDMACopySequence(369)

Figure8-5.PeripheralScatter-Gather,SetupandConfiguration(371)

Figure8-6.PeripheralScatter-Gather,μDMACopySequence(372)

Figure9-1.DigitalI/OPads(422)

Figure9-2.Analog/DigitalI/OPads(423)

Figure9-3.GPIODATAWriteExample(424)

Figure9-4.GPIODATAReadExample(424)

Figure10-1.GPTMModuleBlockDiagram(474)

Figure10-2.TimerDaisyChain(480)

Figure10-3.InputEdge-CountModeExample(482)

Figure10-4.16-BitInputEdge-TimeModeExample(483)

Figure10-5.16-BitPWMModeExample(484)

Figure11-1.WDTModuleBlockDiagram(521)

Figure12-1.ImplementationofTwoADCBlocks(546)

Figure12-2.ADCModuleBlockDiagram(547)

Figure12-3.ADCSamplePhases(551)

Figure12-4.DoublingtheADCSampleRate(552)

Figure12-5.SkewedSampling(552)

Figure12-6.SampleAveragingExample(553)

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Figure12-7.ADCInputEquivalencyDiagram(554)

Figure12-8.InternalVoltageConversionResult(555)

Figure12-9.ExternalVoltageConversionResult(556)

Figure12-10.DifferentialSamplingRange,VIN_ODD=1.5V(557)

Figure12-11.DifferentialSamplingRange,VIN_ODD=0.75V(558)

Figure12-12.DifferentialSamplingRange,VIN_ODD=2.25V(558)

Figure12-13.InternalTemperatureSensorCharacteristic(559)

Figure12-14.Low-BandOperation(CIC=0x0and/orCTC=0x0)(562)

Figure12-15.Mid-BandOperation(CIC=0x1and/orCTC=0x1)(563)

Figure12-16.High-BandOperation(CIC=0x3and/orCTC=0x3)(564)

Figure13-1.UARTModuleBlockDiagram(626)

Figure13-2.UARTCharacterFrame(629)

Figure13-3.IrDADataModulation(631)

Figure13-4.LINMessage(633)

Figure13-5.LINSynchronizationField(634)

Figure14-1.SSIModuleBlockDiagram(690)

Figure14-2.TISynchronousSerialFrameFormat(SingleTransfer)(694)

Figure14-3.TISynchronousSerialFrameFormat(ContinuousTransfer)(694)

Figure14-4.FreescaleSPIFormat(SingleTransfer)withSPO=0andSPH=0(695)

Figure14-5.FreescaleSPIFormat(ContinuousTransfer)withSPO=0andSPH=0(695)

Figure14-6.FreescaleSPIFrameFormatwithSPO=0andSPH=1(696)

Figure14-7.FreescaleSPIFrameFormat(SingleTransfer)withSPO=1andSPH=0(697)

Figure14-8.FreescaleSPIFrameFormat(ContinuousTransfer)withSPO=1andSPH=0(697)

Figure14-9.FreescaleSPIFrameFormatwithSPO=1andSPH=1(698)

Figure14-10.MICROWIREFrameFormat(SingleFrame)(699)

Figure14-11.MICROWIREFrameFormat(ContinuousTransfer)(700)

Figure14-12.MICROWIREFrameFormat,SSIFssInputSetupandHoldRequirements(700)

Figure15-1.I2CBlockDiagram(732)

Figure15-2.I2CBusConfiguration(733)

Figure15-3.STARTandSTOPConditions(734)

5dbd71cb7f1922791688e8bdpleteDataTransferwitha7-BitAddress(734)

Figure15-5.R/SBitinFirstByte(735)

Figure15-6.DataValidityDuringBitTransferontheI2CBus(735)

Figure15-7.MasterSingleTRANSMIT(739)

Figure15-8.MasterSingleRECEIVE(740)

Figure15-9.MasterTRANSMITwithRepeatedSTART(741)

Figure15-10.MasterRECEIVEwithRepeatedSTART(742)

Figure15-11.MasterRECEIVEwithRepeatedSTARTafterTRANSMITwithRepeated

START(743)

Figure15-12.MasterTRANSMITwithRepeatedSTARTafterRECEIVEwithRepeated

START(744)

Figure15-13.SlaveCommandSequence(745)

Figure16-1.I2SBlockDiagram(770)

Figure16-2.I2SDataTransfer(773)

Figure16-3.Left-JustifiedDataTransfer(773)

Figure16-4.Right-JustifiedDataTransfer(773)

Figure17-1.CANControllerBlockDiagram(807)

Figure17-2.CANData/RemoteFrame(809)

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Stellaris?LM3S5P51MicrocontrollerFigure17-3.MessageObjectsinaFIFOBuffer(817)

Figure17-4.CANBitTime(821)

5dbd71cb7f1922791688e8bdBModuleBlockDiagram(858)

Figure19-1.AnalogComparatorModuleBlockDiagram(996)

Figure19-2.StructureofComparatorUnit(998)

5dbd71cb7f1922791688e8bdparatorInternalReferenceStructure(999)

Figure20-1.PWMModuleDiagram(1011)

Figure20-2.PWMGeneratorBlockDiagram(1011)

Figure20-3.PWMCount-DownMode(1015)

Figure20-4.PWMCount-Up/DownMode(1016)

Figure20-5.PWMGenerationExampleInCount-Up/DownMode(1016)

Figure20-6.PWMDead-BandGenerator(1017)

Figure21-1.QEIBlockDiagram(1083)

Figure21-2.QuadratureEncoderandVelocityPrepiderOperation(1086)

Figure22-1.100-PinLQFPPackagePinDiagram(1105)

Figure22-2.108-BallBGAPackagePinDiagram(TopView)(1106)

Figure25-1.LoadConditions(1181)

Figure25-2.JTAGTestClockInputTiming(1182)

Figure25-3.JTAGTestAccessPort(TAP)Timing(1182)

Figure25-4.Power-OnResetTiming(1183)

Figure25-5.Brown-OutResetTiming(1183)

Figure25-6.Power-OnResetandVoltageParameters(1184)

Figure25-7.ExternalResetTiming(RST)(1184)

Figure25-8.SoftwareResetTiming(1184)

Figure25-9.WatchdogResetTiming(1185)

Figure25-10.MOSCFailureResetTiming(1185)

Figure25-11.HibernationModuleTimingwithInternalOscillatorRunninginHibernation(1190)

Figure25-12.HibernationModuleTimingwithInternalOscillatorStoppedinHibernation(1190)

Figure25-13.ADCInputEquivalencyDiagram(1192)

Figure25-14.SSITimingforTIFrameFormat(FRF=01),SingleTransferTiming

Measurement(1193)

Figure25-15.SSITimingforMICROWIREFrameFormat(FRF=10),SingleTransfer(1193)

Figure25-16.SSITimingforSPIFrameFormat(FRF=00),withSPH=1(1194)

Figure25-17.I2CTiming(1195)

Figure25-18.I2SMasterModeTransmitTiming(1195)

Figure25-19.I2SMasterModeReceiveTiming(1196)

Figure25-20.I2SSlaveModeTransmitTiming(1196)

Figure25-21.I2SSlaveModeReceiveTiming(1196)

FigureC-1.StellarisLM3S5P51100-PinLQFPPackageDimensions(1251)

FigureC-2.100-PinLQFPTrayDimensions(1253)

FigureC-3.100-PinLQFPTapeandReelDimensions(1254)

FigureC-4.StellarisLM3S5P51108-BallBGAPackageDimensions(1255)

FigureC-5.108-BallBGATrayDimensions(1257)

FigureC-6.108-BallBGATapeandReelDimensions(1258)

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TableofContents

ListofTables

Table1.RevisionHistory(37)

Table2.DocumentationConventions(47)

Table2-1.SummaryofProcessorMode,PrivilegeLevel,andStackUse(75)

Table2-2.ProcessorRegisterMap(76)

Table2-3.PSRRegisterCombinations(81)

Table2-4.MemoryMap(89)

Table2-5.MemoryAccessBehavior(92)

Table2-6.SRAMMemoryBit-BandingRegions(94)

Table2-7.PeripheralMemoryBit-BandingRegions(94)

Table2-8.ExceptionTypes(100)

Table2-9.Interrupts(101)

Table2-10.ExceptionReturnBehavior(106)

Table2-11.Faults(106)

Table2-12.FaultStatusandFaultAddressRegisters(108)

Table2-13.Cortex-M3InstructionSummary(110)

Table3-1.CorePeripheralRegisterRegions(113)

Table3-2.MemoryAttributesSummary(116)

Table3-3.TEX,S,C,andBBitFieldEncoding(119)

Table3-4.CachePolicyforMemoryAttributeEncoding(120)

Table3-5.APBitFieldEncoding(120)

Table3-6.MemoryRegionAttributesforStellarisMicrocontrollers(120)

Table3-7.PeripheralsRegisterMap(121)

Table3-8.InterruptPriorityLevels(148)

Table3-9.ExampleSIZEFieldValues(176)

Table4-1.JTAG_SWD_SWOSignals(100LQFP)(180)

Table4-2.JTAG_SWD_SWOSignals(108BGA)(181)

Table4-3.JTAGPortPinsStateafterPower-OnResetorRSTassertion(182)

Table4-4.JTAGInstructionRegisterCommands(187)

Table5-1.SystemControl&ClocksSignals(100LQFP)(191)

Table5-2.SystemControl&ClocksSignals(108BGA)(191)

Table5-3.ResetSources(192)

Table5-4.ClockSourceOptions(199)

Table5-5.PossibleSystemClockFrequenciesUsingtheSYSDIVField(202)

Table5-6.ExamplesofPossibleSystemClockFrequenciesUsingtheSYSDIV2Field(202)

Table5-7.ExamplesofPossibleSystemClockFrequencieswithDIV400=1(203)

Table5-8.SystemControlRegisterMap(208)

Table5-9.RCC2FieldsthatOverrideRCCFields(229)

Table6-1.HibernateSignals(100LQFP)(296)

Table6-2.HibernateSignals(108BGA)(297)

Table6-3.HibernationModuleClockOperation(303)

Table6-4.HibernationModuleRegisterMap(305)

Table7-1.FlashMemoryProtectionPolicyCombinations(326)

5dbd71cb7f1922791688e8bder-ProgrammableFlashMemoryResidentRegisters(330)

Table7-3.FlashRegisterMap(330)

Table8-1.μDMAChannelAssignments(361)

Table8-2.RequestTypeSupport(363)

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Stellaris?LM3S5P51MicrocontrollerTable8-3.ControlStructureMemoryMap(364)

Table8-4.ChannelControlStructure(364)

Table8-5.μDMAReadExample:8-BitPeripheral(373)

Table8-6.μDMAInterruptAssignments(374)

Table8-7.ChannelControlStructureOffsetsforChannel30(375)

Table8-8.ChannelControlWordConfigurationforMemoryTransferExample(375)

Table8-9.ChannelControlStructureOffsetsforChannel7(376)

Table8-10.ChannelControlWordConfigurationforPeripheralTransmitExample(377)

Table8-11.PrimaryandAlternateChannelControlStructureOffsetsforChannel8(378)

Table8-12.ChannelControlWordConfigurationforPeripheralPing-PongReceive

Example(379)

Table8-13.μDMARegisterMap(380)

Table9-1.GPIOPinsWithNon-ZeroResetValues(418)

Table9-2.GPIOPinsandAlternateFunctions(100LQFP)(418)

Table9-3.GPIOPinsandAlternateFunctions(108BGA)(420)

Table9-4.GPIOPadConfigurationExamples(426)

Table9-5.GPIOInterruptConfigurationExample(427)

Table9-6.GPIOPinsWithNon-ZeroResetValues(428)

Table9-7.GPIORegisterMap(428)

Table9-8.GPIOPinsWithNon-ZeroResetValues(441)

Table9-9.GPIOPinsWithNon-ZeroResetValues(447)

Table9-10.GPIOPinsWithNon-ZeroResetValues(449)

Table9-11.GPIOPinsWithNon-ZeroResetValues(452)

Table9-12.GPIOPinsWithNon-ZeroResetV