自动化数字逻辑设计课件四章

Chapter4DigitalCircuitsDigitalDesign

—PinciplesandPracticesDigitalDesign

—PinciplesandPracticesLogicSignalsandGatesRepresentationof0/1inPhysicsRefertoTable3-1UsetwooppositestatesUsetransitionsbetweenthetwostatesElectronicstatesarevolatileLogicSignalsandGatesGettingtheHighorLowVoltageVOUTVINVccRTheBasicPrinciplePositiveLogic10NegativeLogic10LogicSignalsandGatesElectronicSwitchesRelayLogicSignalsandGatesElectronicSwitchesVacuumTubesLogicSignalsandGatesElectronicSwitchesDiscreteTransistorBipolarTransistor&MOSFETLogicSignalsandGatesElectronicSwitchesIntegratedCircuitsBipolarIC&CMOSICLogicSignalsandGatesLogicGatesLogicgatesarebetterdigitalcircuitbuildingblocksthanswitches(transistors)LogicFamiliesMOSTTLMetal-oxidesemiconductor(金属氧化物半导体)Transistor-TransistorLogic(晶体管-晶体管逻辑)CMOS

ComplementaryMetal-Oxide-Semiconductor(互补金属氧化物半导体)LowpowerconsumptionLowspeedHighspeedHighpowerconsumptionHighspeedLowpowerconsumptionMOSTransistorsCMOSLogicTwoTypes:N-ChannelandP-ChannelDrain(漏极)Source(源极)Gate(栅极)Vgs+N-Channel(N沟道)Usually：

Vgs>=0

Vgs=0RdsVeryHigh,≈106Ω

Off(截止状态)

Vgs↑

Rds↓

On(导通状态),≈10ΩIgs

(LeakageCurrent)isverysmall,<=1μACapacitiveCoupleIncreasethepowerconsumptioninhigh-speedcircuits.MOSTransistorsCMOSLogicSource(源极)Drain(漏极)Gate(栅极)

+VgsP-Channel(P沟道)Usually：

Vgs<=0

Vgs=0RdsVeryHigh,≈106Ω

Off(截止状态)

Vgs↓

Rds↓

On(导通状态),≈20ΩIgs

(LeakageCurrent)

isverysmall,<=1μACapacitiveCoupleincreasesthepowerconsumptioninhigh-speedcircuits.MOSTransistorsCMOSLogicSDGP-ChannelSDGN-ChannelDN-ChannelSGSDGP-ChannelMorenaturalrepresentationsymbolHigh->OnLow->OnRonofNMOS<RonofPMOSBASICCMOSCircuit——InverterCMOSLogicNMOSandPMOSareusedtogetherinacomplementarywaytoform

CMOSLogic.VIN=0.0VVGSn=0.0V,TnOff(截止)VGSp=VIN–VDD=–5.0V,TpOn(导通)VOUT

≈

VDD=5.0VVIN=VDD=5.0VVGSn=5.0V,TnOn(导通)VGSp=VIN–VDD=0.0V,TpOff(截止)VOUT

≈

0VDD=+5.0VVOUTVINTpTnBASICCMOSCircuit——InverterCMOSLogicSymbolEquationTruthTableAZ0110Z=A’AZANSI,IEEEStandardAZIECStandardAZChinaStandardCMOSNANDGatesCMOSLogicEitherInputLow,ThenEitherT1,T3Off(T1,T3至少有一个截止)EitherT2,T4On(T2,T4至少有一个导通)ZisHigh,≈

VDDBothInputsHigh,ThenBothT1,T3On(T1,T3都导通)BothT2,T4Off(T2,T4都截止)

ZisLow,≈

0VVDD=+5.0VZABT1T3T2T4CMOSNANDGatesCMOSLogicSymbolEquationTruthTableABZ001011101110Z=(A·B)’

ABZANSI,IEEEStandardABZIECStandardABZChinaStandardCMOSNORGatesCMOSLogicBothInputsLow,ThenBothT1,T3Off(T1,T3都截止)BothT2,T4On(T2,T4都导通)ZisHigh,

VDDEitherInputHigh,ThenEitherT1,T3On(T1,T3至少有一个导通)EitherT2,T4Off(T2,T4至少有一个截止)ZisLow,0VVDD=+5.0VZABT1T3T2T4CMOSNORGatesCMOSLogicSymbolEquationTruthTableABZ001010100110Z=(A+B

)’ABZANSI,IEEEStandardABZIECStandardABZChinaStandardNAND

VS

NORCMOSLogicRonofNAND<RonofNORSpeedofNAND>SpeedofNORFan-InCMOSLogicMeansthenumberofinputsthatagatehas.Ann-inputgatehasnseriesandnparalleltransistors.EquationZ=(A·B·C)’

SymbolTruthTable01111011110110011100BACZ001011001011VDD=+5.0VZABCANDPropertyORPropertyFan-InCMOSLogicTheadditive“on”resistanceofseriestransistorslimitstheFan-In.

(导通电阻的可加性限制了CMOS门的扇入数)Typically,4forNORgatesand6forNANDgates.Alargenumberofinputscanbemadebycascadinggateswithfewerinputs.(可用较少输入门级联得到较多的输入)Fasterthanone-level-8-inputNANDNoninvertingGates——BufferCMOSLogicVDD=+5.0VVINVOUTHasdrivingabilitytotransmitfarther

CMOSAND-OR-INVERT(AOI)CMOSLogicABCDVDD=+5.0VZVDD=+5.0VBACDCBADZ?ABCDZ11XX0XX1100X0X10XX01X00X1X0X01ABCDZHowtodrawthelogicdiagram?TruthTableCMOSOR-AND-INVERT(OAI)

CMOSLogicVDD=+5.0VCACABDBDZ?ABCDZ00XX1XX