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Navigatingtheautomotivesemiconductorstrategic

dilemma–makeorbuy?

AntonioRusso

21/03/2024

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Challenges

Off-the-shelfSoCscaterwellformostapplications,sowhyevenconsiderotheravenues?

•Supplychainspredictability

•Fewervendorstochoosefrom

•Costsavings

•Computescalabilitychallenges

•Energyefficiency

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Off-the-shelfsilicondevices

Pros

•Immediateavailability

•Shorttermcostsavings

•Immediateaccesstoexpertise

•Riskmitigation

Cons

•Littletonocustomisation

•NocontroloverIP

•Longtermcost

•Commoditisationofsolutions

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NIOannouncesownSoC

Off–the-shelf

SoC

Higherflexibilitytoworkloads,lessefficient

Custom

SoC

TESLAownFSD

SW/HWco-designoffers

higherintegrationandpower

efficiencyatthecostof

flexibility

Customcomputinginautomotive

Power

efficiency

Flexibility

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Example:

Buildingscalabilityforconvergeddomains

Scalabilityandchallengeofdiesizes

ADAS->

NCAP/L2

L2++

L3

IVIEntry

X

IVIMid

X

X

X

IVIHigh

X

X

Domains’convergence,enhancedUXandhigherADASincreasecomputing

=>higherdiesizes(>200mm2)Defectdensity

Yield

Defectdensity

0.10.20.30.4

100%

80%

60%

40%

20%

0%

10100200300400500600700800

Diesize(a)inmm²

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requirements

*SimplifiedIllustrationbasedonPoissonModel:Y=e–a*d

5

MonolithicSoC&modules

Definition:anentireintegratedcircuitonasinglesemiconductorsubstrate

ECARXAntora

7nm,

90kDMIPS

0.9TFLOPS

8TOPS

ECARXAntoraPro

ECARXSuperBrain

Antora+BSTA1000

7nm,

180kDMIPS

1.8TFLOPS

16TOPS

Fordieareasabove150mm2,monolithicSoCsbecomeincreasinglylesscosteffective

Yet,theyrepresenttheoptimalbalanceofpowerefficiencyorperformance/Watt

Themonolithicapproachisdominanttodayandwilllikelycontinuetoplayakeyrole

•MultiplediscretemonolithicSoCsareoftenusetocombinefunctionality,egIVI&ADAS

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Afuturewithchiplets

Chiplet:Adiscreteunpackageddietobeassembledintoapackagewithotherchipletonacommonsubstrate

RenesasandIntelannounceautomotiveproductssupportingD2Dinterfacesforchiplets

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Whychiplets

Pros

ScalabilityandFlexibility

ImprovedPerformance

EasierUpgradesandMaintenance

InteroperabilityandStandardization

ReducedTime-to-Market

Cons

DesignComplexity

LikelyHigherPowerConsumption

NRECosts

Standardizationmaturity

ReliabilityandFaultIsolation

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Memory

Memory

–leveragefewSoCsthatsupportD2Dinterfacestoaddacceleration

•Notafullchipletapproach,limitedtoadoptingtheframeworkofaSoCvendorandworkwithinitsconstraints

Shortterm

Custom

ChipletLibrary

Memory

Fixed

Custom

SoC

Emergingopportunitiesaroundchiplets

I/F

CPU

Connectivity

AI/ML

GPU

CPU

GPUs

Longerterm

AI/ML

–ecosystemsupplymaturesandmultiplechipletsare

readilyavailableontheopenmarket

•eg,IOs,Interfaces,variouscompute,HBM,etc

•Augmentedwithowncustomdesignsasneeded

CustomDie

9

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Chipletsstandardisationchallenges

MultipleDietoDieinterfaces(D2D)standardsexists,inadditiontoproprietaryinterfaces

•MaincompetingopenstandardsincludeUniversalChipletInterconnectExpressandBunchofWires

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