Vivado从此开始（第2版）课件 16-Virtual-Clock - 20-Design-Analysis-After-Synthesis-PartI

Lauren

GaoVirtual

Clock©Copyright2012XilinxXilinxDesignConstraints-2Clockspecifiedbytheset_input_delayandset_output_delaycanbe

anyclockfromtheclock

databaseManuallycreatedclockattachedtoaclockinputportofthe

FPGADerivedclockgeneratedinsidethe

FPGAThisislegal,butrarely

usefulSometimestheproperclocktousedoesnotalready

existVirtualclockscanbecreatedsolelyforthepurposeofspecifyinginputandoutputdelaysClocksforInputandOutput

DelayMMCMclkIBUFGBUFGclkoutRarelyuseful!©Copyright2012XilinxXilinxDesignConstraints-3ReasonforUsingVirtual

ClockTherearemanyreasonsforusingvirtualclocksforclockingI/ODeviceexternaltotheFPGAusesadifferentclockthanthe

FPGARunsatadifferent

frequencyMaybeamultiple/divisionoftheFPGA

clockMaybethefrequencyofaninternalFPGAclockgeneratedbyan

MMCM/PLLHasadifferentdelaypathonthe

boardMaybehasclockbufferchiponthe

boardXDCprovidespowerfulmechanismsfordescribing

clocksRemember,allclocksinXDCarerelatedby

defaultPrimarilyusedtomodelsystemclocksforIO

timing!VirtualClockforIOTiming–Example

1D QD QMMCMD QD QPrimaryclockInternalclockdinadinbcreate_clock-namesysclk-period10[get_ports

clkin]create_clock-namevclk-period5set_input_delay6–clockclk[get_portsdina]Set_input_delay6–clockvclk[get_ports

dinb]Vclkhassameperiodasinternalclock(MMCMoutput

clock)!XilinxDesignConstraints

-

4 ©Copyright2012

XilinxFPGA©Copyright2012XilinxXilinxDesignConstraints-5VirtualClockforIOTiming–Example

2DTsuThTCOUpstream

Device1nsvirtclksysclk=Q D QPrimaryclockdinaFPGAcreate_clock-namesysclk-period10[get_portsclkin]create_clock-namevirtclk-period10set_clock_latency-source1[get_clocksvirtclk]set_input_delay-clockvirtclk-max4[get_portsain]set_input_delay-clockvirtclk-min2[get_ports

ain]©Copyright2012XilinxXilinxDesignConstraints-6Virtualclocksarecreatedwith

create_clockCreateclockisnotattachedtoanydesign

objectscreate_clock-name<name>-period

<period><period>istheperiodofthe

clock<name>istheuserassignednameforthe

clockCanusethe-waveform

optionCanspecifyjitterwiththeset_input_jitter

commandCansetclocklatencywiththeset_clock_latency-sourcecommandVirtualclocksareplacedinthedesigndatabaseandcanbeaccessedlikeother

clocksCanbeseenviathereport_clocks

commandCanbeaccessedbytheget_clocks

commandCreatingVirtual

Clocks©Copyright2012XilinxXilinxDesignConstraints-7InputStaticTimingPathwithExternal

BufferclkTsuThTCOUpstream

DeviceD QDataPath

DelayTrace

Delaycreate_clock-namesysclk-period10[get_portsclkin]create_clock-namevirtclk-period10set_clock_latency-source1[get_clocksvirtclk]set_input_delay-clockvirtclk-max4[get_portsain]set_input_delay-clockvirtclk-min2[get_portsain]virtclksysclk=Source

ClockDelayDestinationClock

Delay1ns©Copyright2012XilinxXilinxDesignConstraints-8ReportClockforVirtual

Clock©Copyright2012XilinxXilinxDesignConstraints-9InputSetupTimingReportSummarywithVirtual

Clock©Copyright2012XilinxXilinxDesignConstraints-10InputSetupTimingReportDetailedPaths

withVirtual

ClockSourceClock

DelayDataPathDelayDestinationClock

DelaySlack

Calculation©Copyright2012XilinxXilinxDesignConstraints-11InputHoldTimingReportSummarywith

VirtualClock©Copyright2012XilinxXilinxDesignConstraints-12InputHoldTimingReportDetailedPaths

withVirtualClockSourceClock

DelayData

PathDelayDestinationClock

DelaySlack

Calculation©Copyright2012XilinxXilinxDesignConstraints-13Tocompletethestatictimingpathweneedtodescribethe

externalelementstotheVivadostatictiming

engineInputportWhatclockisusedbytheexternal

deviceThedelaybetweentheexternaldevice'sclockandthearrivalattheinputportoftheFPGAIncludestheCLK-Qtimeoftheexternaldeviceandtheboard

delayOutput

portThedelaybetweenoutputportoftheFPGAandtheexternaldevice's

clockIncludestherequiredtimeoftheexternaldeviceandtheboard

delayCompletetheStaticTiming

PathLauren

GaoSettingMulticyclePath

ConstraintRelaxestiming

requirementsSomelogicpathsneedmorethan1

cycletopropagatetonextsequentialcellAllowstoolstofocusonrealcritical

pathsIteffectsbothsetupandhold

timingWhyMulticyclePath

ExceptionsDefaultSetupandHold

Analysis01202Prev

DataHold

EdgeSetupEdge

1Next

DataSetupcheckisperformedat

destination:1

clockcycleafterthelaunchclockedgeHoldcheckisperformedat

destination:1-1=0clockcyclesafterthelaunchclock

edgeSource

ClkDestination

ClkMulticyclePath:An

ExampleREGB/CLK012CaptureDefaultsetup

relationshipNewsetuprelationshipwithmulticyclepath

settingD QCEclkLaunchREGA/CLKcerega Multicycle

Path=

2T regbD QCEMulticyclePath:An

ExampleREGB/CLK0 12CapturesetupholdHoldCheckIsBasedonSetup

Check!D QCED QCEclkTheholdrelationshipshownbesideisprobably

notthecorrectrelationshipforthe

designLaunchREGA/CLKceMulticyclePath=

2TregaregbMulticyclePath:An

ExampleREGB/CLK012CaptureNew

setupDefault

holdNew

holdD QCEclkLaunchREGA/CLKcerega Multicycle

Path

=

2T regbD QCESet_multicycle_pathREGB/CLK0 1LaunchREGA/CLK2

CaptureNew

setupDefault

holdNew

holdset_multicycle_path-from[get_cellsrega]-to[get_cellsrega]–setup-end

2set_multicycle_path-from[get_cellsregb]-to[get_cellsregb]–hold-end

1*语句中数字的含义：对于-setup：表示该多周期路径所需要的时钟周期个数；对于-hold：表示相对于缺省捕获沿（图中的Default

hold）,实际捕获沿（图中的New

hold）应回调的时钟周期个数*参考时钟周期的选取：-end表示参考时钟为捕获端（收端）所用时钟，对于-setup缺省为-end-start表示参考时钟为发送端（发端）所用时钟，对于-hold缺省为-startApp1

:SameFrequencyClockswithDestinationClockPositive

Offset12

CaptureDefault

SCDQD QComb.

Logicclk1FF1FF2HC1NewSC

HC2clk20Launchclk1clk2set_multicycle_path-from[get_clocksclk1]-to[get_clocksclk2]-setup-end

2Inthisexample,thedefaultholdanalysisreturnsthepreferredholdrequirementsandnomulticycleholdexceptionsare

requiredApp2

:SameFrequencyClockswithDestinationClockNegative

OffsetSCDQD Qclk1FF1FF2HC1HC2CaptureInthisexample,thedefaultsetupandholdanalysisreturnsthepreferred

requirementsandnomulticycleexceptionsare

requiredclk20Launchclk1clk2App3

:TheDestinationClockFrequencyisaMultipleoftheSource

ClockFrequencyDQD Qclk1clk2FF1FF20 12CaptureHC1

SCHC2New

HCLaunchclk1clk2set_multicycle_path-from[get_clocksclk1]-to[get_clocksclk2]-setup-end

2set_multicycle_path-from[get_clocksclk1]-to[get_clocksclk2]-hold-end

1App4

:TheSourceClockFrequencyisaMultipleoftheDestination

ClockFrequencyDQD QComb.

Logicclk1clk2FF1FF201Launch2SCHC1HC2New

HCclk1clk2Captureset_multicycle_path-from[get_clocksclk1]-to[get_clocksclk2]-setup-start

2set_multicycle_path-from[get_clocksclk1]-to[get_clocksclk2]-hold-start

1App5:MulticyclePathUsingClock

EnableD QCED QCEceMulticyclePath=

2Tregaregbclksetencells[get_cells-of_objects[get_pins-leaf

–filter\{IS_ENABLE==1}-of_objects[get_nets

CE]]]set_multicycle_path-from$encells-to$encells-setup

2set_multicycle_path-from$encells-to$encells-hold

1Bydefault,thesetuppathmultiplierisdefinedwithrespectto

thedestinationclock

(-end)Bydefault,theholdpathmultiplierisdefinedwithrespecttothesourceclock(-start)The-start/-endoptionshavenoeffectwhenapplyingamulticyclepathconstraintonpathsclockedbythesameclock,orclockedbytwoclockshavingthesamewaveform,orwithnophase

shiftSummaryLauren

GaoSettingFalse

PathWhatisFalse

PathApaththatdoesexistinthedesignbutdoesnotplayapartintheoperation,soit'snotnecessarytoincludeitinthetiming

analysisisnot

functionaldoesnotneedtobe

timedWhyFalsePath

ExceptionsRemoveinvalidtiming

pathsStaticsignalsdrivenbyconfiguration

registersSavetimeand

resourcesSkipfalsepath

optimizationWhatand

Why?set_false_path[-setup][-hold][-rise][-fall]

[-reset_path][-fromargs][-rise_fromargs][-fall_fromargs][-to

args][-rise_toargs][-fall_toargs][-throughargs][-rise_through

args][-fall_throughargs][-quiet]

[-verbose]set_false_pathPathSpecification

#1S1S2S3S4P1P2P3P4X1X2X3X4D1D2D3D4set_false_path–from

S1S1→P1→X1→D1S1→P1→X1→D2S1→P1→X2→D2S1→P1→X2→D3S1→P2→X2→D2S1→P2→X2→D3S1→P2→X3→D3S1→P2→X3→D4set_false_path–through

P1S1→P1→X1→D1S1→P1→X1→D2S1→P1→X2→D2S1→P1→X2→D3S4→P1→X1→D1S4→P1→X1→D2S4→P1→X2→D2S4→P1→X2→D3PathSpecification

#2S1S2S3S4P1P2P3P4X1X2X3X4D1D2D3D4set_false_path–to

D1S1→P1→X1→D1S4→P1→X1→D1set_false_path-fromS1-throughX1S1→P1→X1→D1S1→P1→X1→D2PathSpecification

#3S1S2S3S4P1P2P3P4X1X2X3X4D1D2D3D4set_false_path-fromS1-through{X1,

X2}S1→P1→X1→D1S1→P1→X1→D2S1→P1→X2→D2S1→P1→X2→D3S1→P2→X2→D2S1→P2→X2→

D3set_false_path-fromS1-throughX1set_false_path-fromS1-throughX2PathsstartingfromS1andpassingthrougheitherof(X1orX2

)PathSpecification

#4S1S2S3S4P1P2P3P4X1X2X3X4D1D2D3D4set_false_path-throughP1-through

X1S1→P1→X1→D1S4→P1→X1→

D1S1→P1→X1→D2S4→P1→X1→

D2When-throughisspecifiedmultipletimes,itindicates

thateachofthe–throughhavetobesatisfied

independently-throughP1-through

X1

≠-throughX1-through

P1-through{X1,

X2}

≠-throughX1-through

X2set_false_path-fromCLK1meansallpathsoriginating

fromAllsequentialelementstriggeredby

CLK1Andallinputportsconstrainedwithrespectto

CLK1Transition

Specification-rise_from-fall_from-rise_through-fall_through-rise_to-fall_to-rise:impactsonlyrising

paths-fall:impactsonlyfalling

pathsPathSpecification#4TypesofFalsePaths:CombinationalFalse

PathI0I1OI0I1OMUX0MUX1ABSSset_false_path-from[get_portsA]-through

\[get_pinsmux0/I0]-through[get_pinsmux1/I1]-to[get_ports

B]set_false_path-through[get_pinsMUX0/I0]

\-through[get_pins

MUX1/I1]TypesofFalsePaths:SequentialFalse

PathOI1 I1OMUX0 MUX1A I0 I0BSSclkset_false_path-through[get_pinsMUX0/I0]

\-through[get_pinsMUX1/I0]TypesofFalse

Paths:AsynchronousDomain

CrossingsDQDQDQclkaclkbset_false_path–from[get_clocks

clka]–to

[get_clocksclkb]set_false_path–from[get_clocks

clkb]–to

[get_clocksclka]set_clock_groups-asynchronous-group[get_clocksclka]

\-group[get_clocks

clkb]FalsePathTiming

Reportset_false_path-from[get_ports

rst_pin]report_timing-from[get_ports

rst_pin]Impacton

synthesisItisusuallynotneededtousefalsepathexceptionsduringsynthesisexceptforignoringCDC

pathsImpacton

implementationAlltheimplementationstepsaresensitivetothefalsepathtiming

exceptionFalsePath

ImpactLauren

GaoXDC

Precedence–Complex

designOrganizingtheDesign

ConstraintsRecommended

constraint files–Simple

designAllPhyTiming

(Synth)Timing

(Impl)PhyTiming123+++Top-levelTimingTop-levelPhyIP++Manycoreshavetheirownconstraints/

exceptionsPCIE,MIG,RAM-basedasynchronousFIFOs…Non-nativeIP:Be

careful!VeryeasytodroptheIPconstraintsespeciallyifprovidedas.ngcfilesNativeIP:Constraints

includedSourceswindowinIDE:CompileOrder→

ConstraintsUsereport_compile_order–constraintstoidentifyconstraintfile

sourcesIncludeIP

ConstraintsPage

4ManagingIPConstraint

FilesSomeIPcomewiththeirownXDC

constraints–Example:Theclocking

wizardTheclockingwizardXDCwillbereadbeforetheuserXDCby

default(userconstraintscanoverrideIPdefined

clocksbydefault)Theorderofconstraintfiles

matters!ToreporttheorderofXDCfiles:report_compile_order

–constraintsAlwaysverifytheclocksusing

report_clocksTochangethedefaultprocessing

orderset_propertyset_processing_orderearly|late

IP_XDC_FileIfnecessary,IP_XDC_filescanbe

enabled/disabledDefiningTimingConstraintsinFour

StepsCreate

ClocksPrimaryGeneratedUncertaintycreate_clockcreate_generated_clockset_sytem_jitterset_input_jitterset_clock_uncertaintyset_clock_latencyReportsClock

NetworksCheck

Timingset_input_delayset_output_delayset_clock_groupsset_false_pathset_false_pathset_min/max_delayset_multicycle_pathset_case_analysisset_disable_timingI/O

DelaySystemSource

SYNClock

GroupsCDCASYNExclusiveTiming

Exce.IgnoreMax/minReportsCheck

TimingReport

TimingReportsClock

InteractionCheck

TimingReportsTiming

SummaryReport

TimingThenetdelaymodelingisapproximateanddoesnotreflect

placementconstraintsorcomplexeffectssuchas

congestionThemainobjectiveistoobtainanetlistwhichmeetstiming,orfailsbyasmallamount,withrealisticandsimple

constraintsSynthesisconstraintsmustusenamesfromtheelaborated

netlist,preferablyportsandsequential

cells–Duringelaboration,someRTLsignalscandisappearanditisnotpossibletoattachXDCconstraintsto

themOncesynthesishascompleted,Xilinxrecommendsthatyoureviewthetimingandutilizationreportstovalidatethatthenetlistqualitymeetstheapplicationrequirementsandcanbeusedfor

implementationCreateSynthesis

ConstraintsRTLSynthesis(Timing-Driven)TechnologyMapped

NetlistThesynthesisengineacceptsallXDCcommands,butonlysomehave

areal

effectTimingconstraintsrelatedtosetup/recoveryanalysisinfluencethe

QoRcreate_clock,

create_generated_clockset_input_delay,

set_output_delayset_clock_groups,set_false_path,set_max_delay,

set_multicycle_pathTimingconstraintsrelatedtoholdandremovalanalysisareignoredduringsynthesisset_false_path

-holdset_min_delayset_multicycle_path

-holdCreateSynthesis

ConstraintsXDCisbasedonTclsyntaxandinterpretationrules.LikeTcl,XDCis

asequential

languageVariablesmustbedefinedbeforetheycanbe

used–Similarly,timingclocksmustbedefinedbeforetheycanbeusedinotherconstraintsForequivalentconstraintsthatcoverthesamepathsandhavethesameprecedence,thelastone

appliesRecommendedConstraints

Sequencecreate_clock-nameclk1-period10[get_ports

clk_in]create_clock-nameclk2-period11[get_portsclk_in]WinClock

GroupsFalse

PathMax/minDelay

PathMulticycle

Paths(set_clock_groups)(set_false_path)(set_max/min_delay)(set_multicycle_path)Theprecedenceruleforthefilters,fromhighestto

lowest-from-through

-to-from

-to-from

-through-from-through-to-to-throughTimingExceptions

PriorityLowestHighestLowestHighestMorespecificMorehigher

priorityExampleset_max_delay12-from

[get_clocksclk1]

-to[get_clocksclk2]set_max_delay15-from

[get_clocksclk1]Winset_max_delay4-through[get_pinsinst0/I0]set_max_delay5-through[get_pinsinst0/I0]–through\[get_pinsinst1/I3]WinYoumustavoidusingseveraltimingexceptionsonthesamepaths,sothatthetiminganalysisresultsarenotdependentonpriorityrules,anditiseasiertovalidatetheeffectofyour

constraints√Lauren

GaoDesignAnalysisAfter

SynthesisPartIResourceUtilization

AnalysisClockAnalysisFanoutAnalysisControlSets

AnalysisAgendaGetresourceutilizationby

GUIGetresourceutilizationbyTclGettotalresource

utilizationGettheresourceutilizationofthespecifiedcellsor

pblocksResourceUtilization

AnalysisResourceUtilizationby

GUIOpen

SynthesizedDesignReportUtilizationby

Tclreport_utilization[-filearg][-append][-pblocksargs][-cellsargs][-return_strin