数字逻辑设计 - 触发器 Flip-Flops

触发器

Flip-Flops数字系统设计2Spring

2015

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Lec.

#7复习

时序电路的基本概念触发器本节内容

组合电路和Verilog语言测试数字系统设计3Spring

2015

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Lec.

#7测试（补充）

测试是一个专门用来给电路的HDL模型施加的一个激励的HDL程序，目的是测试和观察其在激励下的响应。典型的测试模块没有输入和输出，加到设计模块用于模拟的输入信号在激励模块中定义为局部reg型数据。显示设计模块的测试输出在激励模块中定义为局部wire型数据。用局部的标识来例化测试的模块。测试模块的HDL格式：

module

test_module_name;

//Declare

local

reg

and

wire

identifiers.

//Instantiate

the

design

module

under

test.

//Specify

a

stopwatch,

using

$finish

to

terminate

the

simulation

//Generate

stimulus,

using

initial

and

always

statements.

//Display

the

output

response

(text

or

graphics

(or

both)).

endmodule数字系统设计4Spring

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#7Sequential

Logic

时序逻辑

Sequential

Circuits

时序电路

Simple

circuits

with

feedback

Latches

(level

sensitive)

–

Storage

elements

that

operate

with

signal

levels

(rather

than

signal

transitions)

are

referred

to

as

latches.

Flip-flops

(edge

sensitive)

(abbreviated

FF)

–

A

flip-flop

is

a

binary

storage

device

capable

of

storing

one

bit

of

information.Timing

Methodologies定时

Cascading级联

flip-flops

for

proper

operation

Clock

skew时钟偏移数字系统设计5C3

value

C1comparatorequal

C2multiplexerreset

open/closedSpring

2015

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#7newmuxcontrolclock

equalcomb.

logic

stateSequential

Circuits

Circuits

with

Feedback

Outputs

=

f(inputs,

past

inputs,

past

outputs)

Basis

for

building

"memory"

into

logic

circuits

Door

combination

lock

is

an

example

of

a

sequential

circuit

–

State

is

memory

–

State

is

an

"output"

and

an

"input"

to

combinational

logic

–

Combination

storage

elements

are

also

memory数字系统设计6Spring

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#7X1X2

•

•

•Xnswitching

networkZ1Z2

•

•

•ZnCircuits

with

Feedback

How

to

control

feedback?

What

stops

values

from

cycling

around

endlessly数字系统设计7Spring

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#7"load""data""stored

value"

Simplest

Circuits

with

Feedback

Two

inverters

form

a

static

memory

cell

Will

hold

value

as

long

as

it

has

power

applied

"1"

"stored

value"

"0"

How

to

get

a

new

value

into

the

memory

cell?

Selectively

break

feedback

path

Load

new

value

into

cell

"remember"数字系统设计8Spring

2015

ZDMC

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Lec.

#7RSQ

Q'RSQS'R'QQ

Q'S'R'

Memory

with

Cross-coupled

Gates

Cross-coupled

NOR

gates

Similar

to

inverter

pair,

with

capability

to

force

output

to

0

(reset=1)

or

1

(set=1)

Cross-coupled

NAND

gates

Similar

to

inverter

pair,

with

capability

to

force

output

to

0

(reset=0)

or

1

(set=0)数字系统设计Setting

the

Latch

(FF)

Pulsing

the

SET

input

to

the

0

state

when

(a)

Q

=

0

prior

to

SET

pulse;(b)

Q

=

1

prior

to

SET

pulse.

Note

that,

in

both

cases,

Q

ends

up

HIGH.9Spring

2015

ZDMC

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#7数字系统设计Resetting

the

Latch

(FF)

Pulsing

the

RESET

input

to

the

LOW

state

when

(a)

Q

=

0

prior

to

RESETpulse;

(b)

Q

=

1

prior

to

RESET

pulse.

In

each

case,

Q

ends

up

low.10Spring

2015

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#711Spring

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#7ResetHoldSetSetResetRace

R

S

Q

\Q数字系统设计100Timing

BehaviorRSQ

Q'数字系统设计12Spring

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#7S00R01Qhold011011unstableState

Behavior

of

R-S

latch

Truth

table

of

R-S

latch

behaviorQ

Q'

0

1Q

Q'

1

0Q

Q'0

0Q

Q'1

1数字系统设计13Spring

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#7Theoretical

R-S

Latch

Behavior

State

Diagram

States:

possible

values

Transitions:

changesbased

on

inputsQ

Q'

0

1Q

Q'

1

0Q

Q'

0

0Q

Q'

1

1SR=00SR=11SR=00SR=10SR=01SR=00SR=10SR=00SR=01SR=11SR=11SR=10SR=01SR=01SR=10SR=11possible

oscillationbetween

states

00

and

11数字系统设计14Observed

R-S

Latch

Behavior

SR=00SR=00Q

Q'

0

1Q

Q'

1

0Very

difficult

to

observe

R-S

latch

in

the

1-1

state

One

of

R

or

S

usually

changes

firstAmbiguously

returns

to

state

0-1

or

1-0

A

so-called

"race

condition"

Or

non-deterministic

transition

SR=10SR=01SR=00SR=10SR=00SR=01SR=01SR=10

SR=11

Q

Q'

0

0SR=11

SR=11

Spring

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#700X110X1数字系统设计15Spring

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#7RQQ'Q(t+∆)RSQ(t)SSRQ(t)Q(t+∆)000001010011110001010011111101XXholdresetsetnot

allowedcharacteristic

equation

Q(t+∆)

=

S

+

R’

Q(t)R-S

Latch

Analysis

Break

feedback

pathQ(t)RS16Spring

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#7

QQ'

R'enable'

S'R

SGated

R-S

Latch

Control

when

R

andS

inputs

matter

Otherwise,

the

slightest

glitch

on

R

or

S

while

enable

is

low

could

causechange

in

valuestoredSetReset

S'

R'

enable'

Q

Q'数字系统设计100数字系统设计17

periodSpring

2015

ZDMC

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Lec.

#7Clocks

Used

to

keep

time

Wait

long

enough

for

inputs

(R'

and

S')

to

settle

Then

allow

to

have

effect

on

value

storedClocks

are

regular

periodic

signals

Period

(time

between

ticks)

Duty-cycle

(time

clock

is

high

between

ticks

-

expressed

as

%

of

period)

duty

cycle

(in

this

case,

50%)Q'数字系统设计18

clockSpring

2015

ZDMC

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Lec.

#7R'

and

S'Clocks

(cont’d)

Controlling

an

R-S

latch

with

a

clock

Can't

let

R

and

S

change

while

clock

is

active

(allowing

R

and

S

to

pass)

Only

have

half

of

clock

period

for

signal

changes

to

propagate

Signals

must

be

stable

for

the

other

half

of

clock

period

Qstable

c

hanging

stable

c

hanging

stable

R'clock'

S'R

S19Spring

2015

ZDMC

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Lec.

#7

clock数字系统设计RSQ'

QRSQ'

QRSCascading

Latches

Connect

output

of

one

latch

to

input

of

anotherHow

to

stop

changes

from

racing

through

chain?

Need

to

control

flow

of

data

from

one

latch

to

the

next

Advance

from

one

latch

per

clock

period

Worry

about

logic

between

latches

(arrows)

that

is

too

fast20Spring

2015

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Lec.

#7Master-Slave

Structure

Break

flow

by

alternating

clocks

(like

an

air-lock)

Use

positive

clock

to

latch

inputs

into

one

R-S

latch

Use

negative

clock

to

change

outputs

with

another

R-S

latchView

pair

as

one

basic

unit

master-slave

flip-flop

twice

as

much

logic

output

changes

a

few

gate

delays

after

the

falling

edge

of

clock

but

does

not

affect

any

cascaded

flip-flopsmaster

stageslave

stageP'P

CLK数字系统设计RSQ'

QRSQ'

QRSRRQ'21Set

1scatch

S

R

CLK

P

P'

Q

Q'数字系统设计Reset

Master

Outputs

Slave

OutputsSpring

2015

ZDMC

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Lec.

#7The

1s

Catching

Problem

In

first

R-S

stage

of

master-slave

FF

0-1-0

glitch

on

R

or

S