静态时序分析基本原理和时序分析模型

Quartus®IISoftwareDesignSeries:TimingAnalysis-Timinganalysisbasics2ObjectivesDisplayacompleteunderstandingoftiminganalysis3Howdoestimingverificationwork?Everydevicepathindesignmustbeanalyzedwithrespecttotimingspecifications/requirementsCatchtiming-relatederrorsfasterandeasierthangate-levelsimulation&boardtestingDesignermustentertimingrequirements&exceptionsUsedtoguidefitterduringplacement&routingUsedtocompareagainstactualresults

INCLKOUTDQCLRPREDQCLRPREcombinationaldelays

CLR4TimingAnalysisBasicsLaunchvs.latchedgesSetup&holdtimesData&clockarrivaltimeDatarequiredtimeSetup&holdslackanalysisI/OanalysisRecovery&removalTimingmodels5Path&AnalysisTypesThreetypesofPaths:ClockPathsDataPathAsynchronousPaths*ClockPathsAsyncPathDataPathAsyncPathDQCLRPREDQCLRPRETwotypesofAnalysis:Synchronous –clock&datapathsAsynchronous* –clock&asyncpaths*Asynchronousreferstosignalsfeedingtheasynchronouscontrolportsoftheregisters6Launch&LatchEdgesCLKLaunchEdgeLatchEdgeDataValidDATALaunchEdge: theedgewhich“launches”thedatafromsourceregisterLatchEdge: theedgewhich“latches”thedataatdestinationregister(withrespecttothelaunchedge,selectedbytiminganalyzer;typically1cycle)7Setup&HoldSetup: Theminimumtimedatasignalmustbestable BEFOREclockedgeHold: Theminimumtimedatasignalmustbestable AFTERclockedgeDQCLRPRECLKThValidDATATsuCLKDATATogether,thesetuptimeandholdtimeformaDataRequiredWindow,thetimearoundaclockedgeinwhichdatamustbestable.8DataArrivalTimeDataArrivalTime=launchedge+Tclk1+Tco+TdataCLKREG1.CLKTclk1DataValidREG2.DTdataLaunchEdgeDataValidREG1.QTcoThetimefordatatoarriveatdestinationregister’sDinputREG1PREDQCLRREG2PREDQCLRComb.LogicTclk1TCOTdata9ClockArrivalTimeClockArrivalTime=latchedge+Tclk2

CLKREG2.CLKTclk2LatchEdgeThetimeforclocktoarriveatdestinationregister’sclockinputREG1PREDQCLRREG2PREDQCLRComb.LogicTclk210DataRequiredTime-SetupDataRequiredTime=ClockArrivalTime-Tsu-SetupUncertaintyCLKREG2.CLKTclk2LatchEdgeTheminimumtimerequiredforthedatatogetlatchedintothedestinationregisterTsuDataValidREG2.DDatamustbevalidhereREG1PREDQCLRREG2PREDQCLRComb.LogicTclk2Tsu11DataRequiredTime-HoldDataRequiredTime=ClockArrivalTime+Th+HoldUncertaintyCLKREG2.CLKTclk2LatchEdgeTheminimumtimerequiredforthedatatogetlatchedintothedestinationregisterThDatamustremainvalidtohereDataValidREG2.DREG1PREDQCLRREG2PREDQCLRComb.LogicTclk2Th12Tclk2SetupSlackREG2.CLKThemarginbywhichthesetuptimingrequirementismet.Itensureslauncheddataarrivesintimetomeetthelatchingrequirement.TsuCLKREG1.CLKTclk1DataValidREG2.DTdataDataValidREG1.QTco

SetupSlackLaunchEdgeLatchEdgeREG1PREDQCLRREG2PREDQCLRComb.LogicTclk1TCOTdataTclk2Tsu13SetupSlack(cont’d)PositiveslackTimingrequirementmetNegativeslackTimingrequirementnotmetSetupSlack=DataRequiredTime –DataArrivalTime14HoldSlackREG2.CLKTclk2Themarginbywhichtheholdtimingrequirementismet.Itensureslatchdataisnotcorruptedbydatafromanotherlaunchedge.ThCLKREG1.CLKTclk1DataValidREG2.DTdataDataValidREG1.QTcoHoldSlackLatchEdgeNextLaunchEdgeREG1PREDQCLRREG2PREDQCLRComb.LogicTclk1TCOTdataTclk2Th15HoldSlack(cont’d)PositiveslackTimingrequirementmetNegativeslackTimingrequirementnotmetHoldSlack=DataArrivalTime –DataRequiredTime16FPGA/CPLDorASSPASSPorFPGA/CPLDI/OAnalysisAnalyzingI/OperformanceinasynchronousdesignusesthesameslackequationsMustincludeexternaldevice&PCBtimingparametersreg1PREDQCLRreg2PREDQCLRCL*TdataTclk1Tclk2TCOTsu/ThOSCDataArrivalPathDataArrivalPathDataRequiredPath*Representsdelayduetocapacitiveloading17Recovery&RemovalRecovery: Theminimumtimeanasynchronoussignalmust bestableBEFOREclockedgeRemoval: Theminimumtimeanasynchronoussignalmust bestableAFTERclockedgeDQCLRSETCLKTremValidASYNCTrecCLKASYNC18Asynchronous=Synchronous?AsynchronouscontrolsignalsourceisassumedsynchronousSlackequationsstillapplydataarrivalpath=asynchronouscontrolpathTsu

≈Trec;Th

≈TremExternaldevice&boardtimingparametersmaybeneeded(Ex.1)ASSPreg1PREDQCLRFPGA/CPLDreg2PREDQCLROSCFPGA/CPLDreg1PREDQCLRreg2PREDQCLRExample1Example2DataarrivalpathDataarrivalpathDatarequiredpathDatarequiredpath19WhyAreTheseCalculationsImportant?CalculationsareimportantwhentimingviolationsoccurNeedtobeabletounderstandcauseofviolationExamplecausesDatapathtoolongRequirementtooshort(incorrectanalysis)

Largeclockskewsignifyingagatedclock,etc.TimeQuesttiminganalyzerusesthemEquationstocalculateslackTerminology(launchandlatchedges,DataArrivalPath,DataRequiredPath,etc.)intimingreports20TimingModelsinDetailQuartusIIsoftwaremodelsdevicetimingattwoPVTconditionsbydefaultSlowCornerModelIndicatesslowestpossibleperformanceforanysinglepathTimingforslowestdeviceatmaximumoperatingtemperatureandVCCMINFastCornerModelIndicatesfastestpossibleperformanceforanysinglepathTimingforfastestdeviceatminimumoperatingtemperatureandVCCMAXWhytwocornertimingmodels?EnsuresetuptimingismetinslowmodelEnsureholdtimingismetinfastmodelEssentialforsourcesynchronousinterfacesThirdmodel(slow,min.temp.)availableonlyfor65nmandsmallertechnologydevices(temperatureinversionphenomenon)21GeneratingFast/SlowNetlistSpecifyoneofthedefaulttimingmodelstobeusedwhencreatingyournetlistDefaultistheslowtimingnetlistTospecifyfasttimingnetlistUse-fast_modeloptionwithcreate_timing_netlistcommandChooseFastcornerinGUIwhen executingCreateTimingNetlist

fromNetlistmenuCANNOTselectfastcorner fromTasksPane22SpecifyingOperatingConditionsPerformtiminganalysisfordifferentdelaymodelswithoutrecreatingtheexistingtimingnetlistTakesprecedenceoveralreadygeneratednetlistRequiredforselectingslow,min.temp.modelandothermodels(industrial,military,etc.)dependingondeviceUseget_available_operating_conditionstoseeavailableconditionsfortargetdeviceReferenceDocumentsQuartusIIHandbook,Volume3,Chapter7TheQuartusIITimeQuestTimingAnalyzerQuickStartTutorialCookbookReferenceDocumentsSDCandTimeQuestAPIReferenceManualAN481:ApplyingMulticycleExceptionsintheTimeQuestTimingAnalyzerAN433:ConstrainingandAnalyzingSource-SynchronousInt