VHDL语言语言时序逻辑电路设计课件

VHDL語言語言時序邏輯電路設計

時鐘的描述方法上升沿：CP’EVENTANDCP=‘1’下升沿：CP’EVENTANDCP=‘0’CP=0CP=0CP=1CP=1CP’EVENTCP’EVENTCP’EVENT上升沿D觸發器描述方法一：使用信號屬性函數LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYD_regIS PORT(D,CP:INSTD_LOGIC; Q:OUTSTD_LOGIC);ENDD_reg;ARCHITECTUREtestOFD_regISBEGIN PROCESS(CP) BEGIN

IF(CP’EVENTANDCP=‘1’)THEN Q<=D; ENDPROCESS;ENDtest;方法二：使用WAIT語句LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYD_regIS PORT(D,CP:INSTD_LOGIC; Q:OUTSTD_LOGIC);ENDD_reg;ARCHITECTUREtestOFD_regISBEGIN PROCESS BEGIN

WAITUNTILCP=‘1’; Q<=D; ENDPROCESS;ENDtest;上升沿D觸發器描述方法三：使用上升沿檢測函數LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYD_regIS PORT(D,CP:INSTD_LOGIC; Q:OUTSTD_LOGIC);ENDD_reg;ARCHITECTUREtestOFD_regISBEGIN

PROCESS(cp) BEGIN

IF(rising_edge(cp))THEN Q<=D; ENDIF;

ENDPROCESS;ENDtest;上升沿D觸發器描述方法四：使用進程的啟動特性LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYD_regIS PORT(D,CP:INSTD_LOGIC; Q:OUTSTD_LOGIC);ENDD_reg;ARCHITECTUREtestOFD_regISBEGIN PROCESS（CP） BEGIN

IFCP=‘1’THEN Q<=D; ENDIF; ENDPROCESS;ENDtest;上升沿D觸發器描述上升沿D觸發器描述下降沿D觸發器描述方法一：使用信號屬性函數LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYD_regIS PORT(D,CP:INSTD_LOGIC; Q:OUTSTD_LOGIC);ENDD_reg;ARCHITECTUREtestOFD_regISBEGIN PROCESS(CP) BEGIN

IF(CP’EVENTANDCP=‘0’)THEN Q<=D; ENDPROCESS;ENDtest;方法二：使用WAIT語句LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYD_regIS PORT(D,CP:INSTD_LOGIC; Q:OUTSTD_LOGIC);ENDD_reg;ARCHITECTUREtestOFD_regISBEGIN PROCESS BEGIN

WAITUNTILCP=‘0’; Q<=D;

ENDPROCESS;ENDtest;下降沿D觸發器描述方法三：使用下降沿檢測函數LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYD_regIS PORT(D,CP:INSTD_LOGIC; Q:OUTSTD_LOGIC);ENDD_reg;ARCHITECTUREtestOFD_regISBEGIN

PROCESS(cp) BEGIN

IF(falling_edge(cp))THEN Q<=D; ENDIF;

ENDPROCESS;ENDtest;下降沿D觸發器描述方法四：使用進程的啟動特性LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYD_regIS PORT(D,CP:INSTD_LOGIC; Q:OUTSTD_LOGIC);ENDD_reg;ARCHITECTUREtestOFD_regISBEGIN PROCESS（CP） BEGIN

IFCP=‘0’THEN Q<=D; ENDIF; ENDPROCESS;ENDtest;下降沿D觸發器描述下降沿D觸發器描述髙電平D觸發器描述方法：使用進程的啟動特性LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYD_regIS PORT(D,CP:INSTD_LOGIC; Q:OUTSTD_LOGIC);ENDD_reg;ARCHITECTUREtestOFD_regISBEGIN PROCESS（CP，D） BEGIN

IFCP=‘1’THEN Q<=D; ENDIF; ENDPROCESS;ENDtest;髙電平D觸發器描述低電平D觸發器描述方法：使用進程的啟動特性LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYD_regIS PORT(D,CP:INSTD_LOGIC; Q:OUTSTD_LOGIC);ENDD_reg;ARCHITECTUREtestOFD_regISBEGIN PROCESS（CP，D） BEGIN

IFCP=‘0’THEN Q<=D; ENDIF; ENDPROCESS;ENDtest;低電平D觸發器描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYD_regIS

PORT(d,clk,clr:INSTD_LOGIC;

q:OUTSTD_LOGIC);ENDD_reg;ARCHITECTUREtestOFD_regISBEGIN PROCESS(clk,clr) BEGIN IFclr='1'THEN q<='0'; ELSIFclk'EVENTANDclk='1'THEN q<=d; ENDIF; ENDPROCESS;ENDtest;非同步複位D觸發器非同步複位D觸發器ARCHITECTUREtestOFD_regISBEGIN PROCESS(clk) BEGIN IFclk'EVENTANDclk='1'THEN IFclr='1'THEN q<='0'; ELSE q<=d; ENDIF; ENDIF; ENDPROCESS;ENDtest;同步複位D觸發器同步複位D觸發器例：設計一非同步清零、同步置數的同步8421BCD碼計數器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCOUNT10IS

PORT(CLK,R,S:INSTD_LOGIC; DATA :INSTD_LOGIC_VECTOR(3DOWNTO0); CO :OUTSTD_LOGIC; Q:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0));ENDCOUNT10;時序電路設計舉例ARCHITECTUREtestOFCOUNT10ISBEGIN CO<='1'WHEN(Q="1001")ELSE'0';

PROCESS(CLK,R)

BEGIN

IF(R='0')TH