集成电路的基本制造工艺

上节课内容要点双极集成电路的基本工艺双极集成电路中元件结构2026/9/9pn+n-epin+P-Sin+-BLCBESP+P+双极集成电路的基本工艺2026/9/9P-SiTepiCBEpn+n-epin+P-SiP+P+Sn+-BLTepiAA’TBL-uptepi-oxxmcxjc四层三结结构的双极晶体管双极集成电路中元件结构2026/9/9ECB相关知识点隐埋层的作用、电隔离的概念、寄生晶体管本节课内容

MOS集成电路的工艺

P阱CMOS工艺

BiCMOS集成电路的工艺

N阱CMOS工艺双阱CMOS工艺2026/9/9MOS晶体管的动作

MOS晶体管实质上是一种使电流时而流过，时而切断的开关n+n+P型硅基板栅极（金属）绝缘层（SiO2）半导体基板漏极源极N沟MOS晶体管的基本结构源极(S)漏极(D)栅极(G)MOSFET的基本结构2026/9/9siliconsubstratesourcedraingateoxideoxidetopnitridemetalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongatedopedsiliconfieldoxidegateoxideMOS晶体管的立体结构2026/9/9在硅衬底上制作MOS晶体管siliconsubstrate2026/9/9siliconsubstrateoxidefieldoxide2026/9/9siliconsubstrateoxidephotoresist2026/9/9ShadowonphotoresistphotoresistExposedareaofphotoresistChromeplatedglassmaskUltravioletLightsiliconsubstrateoxide2026/9/9非感光区域siliconsubstrate感光区域oxidephotoresist2026/9/9Shadowonphotoresistsiliconsubstrateoxidephotoresistphotoresist显影2026/9/9siliconsubstrateoxideoxidesiliconsubstratephotoresist腐蚀2026/9/9siliconsubstrateoxideoxidesiliconsubstratefieldoxide去胶2026/9/9siliconsubstrateoxideoxidegateoxidethinoxidelayer2026/9/9siliconsubstrateoxideoxidepolysilicongateoxide2026/9/9siliconsubstrateoxideoxidegategateultra-thingateoxidepolysilicongate2026/9/9siliconsubstrateoxideoxidegategatephotoresistScanningdirectionofionbeamimplantedionsinactiveregionoftransistorsImplantedionsinphotoresisttoberemovedduringresiststrip.sourcedrainionbeam2026/9/9siliconsubstrateoxideoxidegategatesourcedraindopedsilicon2026/9/9自对准工艺在有源区上覆盖一层薄氧化层淀积多晶硅，用多晶硅栅极版图刻蚀多晶硅以多晶硅栅极图形为掩膜板，刻蚀氧化膜离子注入2026/9/9siliconsubstratesourcedraingate2026/9/9siliconsubstrategatecontactholesdrainsource2026/9/9siliconsubstrategatecontactholesdrainsource2026/9/9完整的简单MOS晶体管结构siliconsubstratesourcedraingateoxideoxidetopnitridemetalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongatedopedsiliconfieldoxidegateoxide2026/9/9CMOSFETP型sisubn+gateoxiden+gateoxideoxidep+p+2026/9/9主要的CMOS工艺VDDP阱工艺N阱工艺双阱工艺P-P+P+N+N+P+N+VSSVOUTVINVDDN-P+P+N+N+P+N+VSSVOUTVINVDDP-P+P+N+N+P+N+VSSVOUTVINN-SiP-SiN-I-SiN+-Si2026/9/9掩膜1：P阱光刻P-wellP-well

N+

N+

P+

P+

N+

P+N-SiP2026/9/9具体步骤如下：1．生长二氧化硅（湿法氧化）：Si(固体)+2H2OSiO2（固体）+2H22026/9/9氧化2026/9/92．P阱光刻：涂胶腌膜对准曝光光源显影2026/9/92026/9/9硼掺杂（离子注入）刻蚀（等离子体刻蚀）去胶P+去除氧化膜P-well3．P阱掺杂：2026/9/92026/9/9离子源高压电源电流积分器离子束2026/9/9掩膜2：光刻有源区有源区：nMOS、PMOS

晶体管形成的区域P+N+N+P+N-SiP-wellP-wellP-well淀积氮化硅光刻有源区场区氧化去除有源区氮化硅及二氧化硅SiO2隔离岛2026/9/9有源区depositednitridelayer有源区光刻板N型p型MOS制作区域(漏-栅-源)2026/9/9P-well1.淀积氮化硅：氧化膜生长（湿法氧化）P-well氮化膜生长P-well涂胶P-well对版曝光有源区光刻板2.光刻有源区：2026/9/9P-well显影P-well氮化硅刻蚀去胶3.场区氧化：P-well场区氧化（湿法氧化）P-well去除氮化硅薄膜及有源区SiO22026/9/9掩膜3：光刻多晶硅P-well去除氮化硅薄膜及有源区SiO2P-wellP+N+N+P+N-SiP-well栅极氧化膜多晶硅栅极生长栅极氧化膜淀积多晶硅光刻多晶硅2026/9/9P-well生长栅极氧化膜P-well淀积多晶硅P-well涂胶光刻多晶硅光刻板P-well多晶硅刻蚀2026/9/9掩膜4

：P+区光刻

1、P+区光刻

2、离子注入B+，栅区有多晶硅做掩蔽，称为硅栅自对准工艺。

3、去胶P-wellP+N+N+P+N-SiP-wellP-wellP+P+2026/9/9P-wellP+P-wellP+P+硼离子注入去胶2026/9/9掩膜5

：N+区光刻

1、N+区光刻

2、离子注入P+，栅区有多晶硅做掩蔽，称为硅栅自对准工艺。

3、去胶P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+2026/9/9P-wellN+P-wellP+P+磷离子注入去胶P+P+N+N+2026/9/9掩膜6

：光刻接触孔1、淀积PSG.2、光刻接触孔3、刻蚀接触孔P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+磷硅玻璃（PSG)2026/9/9掩膜6

：光刻接触孔P-wellP+P+N+N+淀积PSGP-wellP+P+N+N+光刻接触孔P-wellP+P+N+N+刻蚀接触孔P-wellP+P+N+N+去胶2026/9/92026/9/9掩膜7

：光刻铝线1、淀积铝.2、光刻铝3、去胶P-wellP-wellP+P+N+N+2026/9/9P-wellP+P+N+N+铝线PSG场氧栅极氧化膜P+区P-wellN-型硅极板多晶硅N+区2026/9/9Example:Intel0.25micronProcess5metallayersTi/Al-Cu/Ti/TiNPolysilicondielectric2026/9/9InterconnectImpactonChip2026/9/9掩膜8

：刻钝化孔CircuitPADCHIP双阱标准CMOS工艺P+p-epipwellnwellp+n+gateoxideAl(Cu)tungstenSiO2SiO2TiSi2fieldoxide增加器件密度防止寄生晶体管效应（闩锁效应）p-epiP阱n+STITiSi2STI深亚微米CMOS晶体管结构STISTISTIN阱n-n+n-p+p-p+p-源/漏扩展区浅槽隔离侧墙多晶硅硅化物2026/9/9功耗驱动能力CMOS双极型Bi-CMOSBiCMOS集成电路工艺2026/9/9BiCMOS工艺分类以CMOS工艺为基础的BiCMOS工艺以双极工艺为基础的BiCMOS工艺。2026/9/9以P阱CMOS工艺为基础的BiCMOS工艺NPN晶体管电流增益小；集电极的串联电阻很大;NPN管C极只能接固定电位，从而限制了NPN管的使用2026/9/9以N阱CMOS工艺为基础的BiCMOS工艺NPN具有较薄的基区，提高了其性能；N阱使得NPN管C极与衬底隔开，可根据电路需要接电位集电极串联电阻还是太大，影响双极器件的驱动能力在现有N阱CMOS工艺上增加一块掩膜板2026/9/9

以N阱CMOS工艺为基础的改