AllegroPCB数字信号完整性.ppt

1、1,AbouttheAuthor,JuergenFlammSeniorTechnicalSalesLeaderCadenceDesignSystems,JuergenholdsaMSEEdegreefromthe“UniversityFridericiana”inKarlsruhe(Germany)Throughouthiscareer,hehasbeenactivelyinvolvedatalllevelsandinallaspectsofelectronicdesign.Hestarteddesigningwidebandtelephonylineamplifiersandrepeater

2、satAEGTelefunken.NexthejoinedLitef(LittonGermany)astheleadengineerforsensorelectronicdevelopment.Hedesignedmixedmodeanalog/digitalASICs,miniaturizedhybridelectronicsandnextlevelmulti-boardsysteminaboxelectronics.HerelocatedtotheUnitedStatesin1990tojoinLittoncorporateastheleaderofaninternationaltechn

3、ologytransferteam.Shortlyafter,hewaspromotedtomanageroftheAnalogDesignGrouptomoveontomanageroftheElectronicEngineeringDepartment.Withthebeginningof2001,aplannedcareerrchangebroughtJuergentoCadence.HejoinedPSDasaSeniorTechnicalSalesLeaderwithfocusontheAllegroPCBSIfamilyoftools.Heholds5patentsintheare

4、asofperformanceelectronicsforfiberopticandMEMSsensors.,2,Agenda,IntroductionDescribingtheproblemDevelopingaSolutionStep1:PowerdeliverysystemanalysisforaboardusingAllegroPCBPIStep2:Powerdeliverysystemanalysisforaboard/packagecombinationusingAllegroPCBSISSNStep3:CombiningStep1andStep2andmoreSummaryQ&A

5、,3,Introduction,Todayshighspeedcircuits,operatingatfastedgerates(100MHz),combinedwithdecreasingsupplyvoltageandincreasingsupplycurrentdemands,havebeenplacinggrowingchallengesonthedesignofpowerdeliverysystems.ThispresentationwillshowhowAllegroPCBSIcanbeutilizedtoperformpost-layoutanalysisofthepowerde

6、liverysystemofacompletedboarddesign(seeICU2003paper#2fordetails).Post-layoutanalysisisonlyoneusemodelofAllegroPCBSI.Thetoolsrealpowerwillbeexperiencedwhenalsoproactivelyemployedforpre-layoutdesignandanalysisaswellasforfloorplanningofapowerdeliverysystem.However,theseusemodelsarenotsubjectofthisprese

7、ntation.,4,DescribingtheProblem,Example:,ParasiticelementsinthePWR/GNDsupplypathcausepowersupplynoiseandfluctuationsonthechipsupplyrails,5,DescribingtheProblem(cont.),MultipleelementsmustbeconsideredsimultaneouslywhenanalyzingaboardsPWR/GNDpathfrompowersourcetothechipsupplyrails.Boardpowersource(VRM

8、)Outputcurrentslewratecapability,dynamicsourceimpedance,BoardplanestructuresDifferentialandcommonmodeimpedance,resonances,BoarddecouplingcapacitorsType,quantity,pinescapeandviaconnections,placementlocation,-BoardtracesandassociatedviasInterconnectingPWR/GNDplanesandchippackagepins,Packagemodel(chip)

9、Pins,traces,planes,vias,bondwires,6,Developingasolution,Step1AnalyzeaboardsPWR/GNDplanepairsimpedance,includingdecouplingcapacitors,usingAllegroPCBPIfrequencydomainsimulation.Step2AnalyzethePWR/GNDconnectionpathfromplanestothechippowerrailsusingAllegroPCBSISSNtimedomainsimulation.Step3AppendStep2mod

10、elwithStep1sourceimpedancemodel.UseappendedmodelandAllegroPCBSISSNsimulationtoevaluatePWR/GNDbounceimpactonsignalwaveformandtiming.,7,Step1,AllegroPCBPIPrepareboardforandrunAllegroPCBPIfrequencydomainsimulationsCompleteAllegroPCBSI“SetupAdvisor”,focuson“IdentifyDCNets”CompleteAllegroPCBPI“SetupWizar

11、d”,selectatleast1standardlibrarycapacitorUse“Report”toidentifycapacitortypesperplanepairCreate/assignmodelsfor/toidentifiedcapacitortypesUnder“CapLibraries”inBoardFolderandselectusedcapacitortypesApproximatemaximumworstcaseswitchingcurrent,placenoisesourceDetermineVRMmodelparametersandplaceVRMSetpre

12、ferencesandrunmultinodesimulationsAnalyzeresultingimpedancegraphsOptionallydetermineasimpleworstcasesourceimpedancemodel(R,L,C),8,Step1,Design&Analysis,Report,LibrarySetup,9,Step1,BoardwithhighlightedPlaneShapes,VRM,NoiseSource,GridSize,10,Step1,MultiNodeSimulationresult,Simplesourceimpedanceapproxi

13、mation:Z=40mOhm+j2pi*f*0.32nH,11,Step2,AllegroPCBSI-SSNPrepareboardforandrunAllegroPCBSISSNtimedomainsimulationsUseAllegroPCBSI“SetupAdvisor”,focuson“DeviceSetup”and“SIModelassignment”ChecktargeteddevicemodelforpinparasiticvaluesAssignpowerbustoassociatedpowerpinsofdevicemodelAssigngroundbustoassoci

14、atedgroundpinsofdevicemodelAssignpowerandgroundbustodesiredsimultaneouslyswitchingI/OpinsofdevicemodelSelectpreferencesasintendedandrunAllegroPCBSISSNsimulationtocreatewaveforms,12,Step2,Power&groundbusassignments,Pindata,Alargepackagemodelinsteadofpindatacouldbeusedtoprovideamorecomprehensivemodel.

15、,Devicemodelpreparation,13,Step2,Powerandgroundbouncewaveforms,14,Step2,AdditionalsignalwaveformevaluationoptionsExtractnetintoAllegroPCBSI210(SigXp)tool,addcurrentprobeandperformreflectionsimulationEvaluatesinglenetvoltageandcurrentwaveformsHelpfultodetermine/validaterise/falltimesandmaximumswitchi

16、ngcurrentusedinstep1SetupandrunEMIsimulationEvaluatesinglenetspectralcurrentdistributionHelpfultodetermineneededbandwidthfortargetimpedanceinstep1,15,Step2,Extractednetwithcurrentprobe,Drivervoltagewaveform,Drivercurrentwaveform,Spectralcurrentdistribution,16,Step3,AllegroPCBSISSNwithaddedsimplesour

17、ceimpedancemodelparametersfromStep1UseRandLmodelfromStep1(slide11)DivideRandLinhalfandaddthevaluestoeachpowerandgroundpinsparasiticvaluesinthedevicemodel.OtheroptionsAddtolargepackagemodelparametersCombineStep1andStep2netlists,17,Step3,ComparisonofAllegroPCBSI-SSNsimulationswithandwithoutadditionals

18、ourceimpedancemodeladdedtopinparameters,18,Step3,MorePerformingacomparisonbetweenReflectionandSSNsimulationresults.EvaluatepowerandgroundbounceimpactonasignalswaveformEvaluatepowerandgroundbounceimpactonasignalstimingEvaluate,19,Step3,Reflection/SSNsimulationcomparison,Fallingedgedetail,20,Summary,UsingAllegroPCBSI,wehavebrieflyintroducedoptionstoperformpost-layoutanalysisofapowerdeliverypathfrompowersourcetothechip