载板制程封装介绍PPT

1、蘇州群策科技公司,載板封裝介紹,電子構裝基礎概念,內容： 構裝技術簡介 最近十年之IC構裝 資料來源：呂宗興 Cell phone ：0932-936-106 clu0563.tw,電子構裝之定義及範圍,定義： 微電子技術之發展日新月異， 電子零組件之尺寸不斷縮小， 零組件之間必須透過高效能、 高可靠性、 高密度及低成本之互連 ( Interconnection )，才能建構成一個具有廣泛性功能及實用價值之電子產品； 而建構此互連技術之相關工程技藝，被統合稱為電子構裝技術。 應用產品：電腦、通訊、電子消費性產品 所需技術 電子、機械、物理、化學、材料、光學、可靠性工程、人因工程等多重之工程技術

2、。,電子構裝之分級,晶圓(Wafer) 晶片(Chip) 第一階層封裝 第二階層封裝 第三階層封裝,單晶片構裝 多晶片模組 ( MCM ： Multi-Chips Module ),模組板 Module board,主機板(母板) Mother board,電子構裝之主要功能,有效供應電源 提供信號傳輸 協助排除耗熱 保護電子零件 建構人機介面,常見之封裝形式,二面出腳 四面出腳,DIP 挿件式 ( Dual In-Line Package ) SOP SMD device ( Small Outline Package ) SOJ ( Small Outline J-Lead ),PLCC

3、( Plastic Leaded Chip Carrier ) QFP ( Quad Flat Pack ) PGA ( Pin Grid Array ),PBGA (Plastic ball Grid Array),單晶片構裝之基本結構,膠體 ( Epoxy Molding Compound ),優點：膠體對稱，不易產生翹曲,晶片(Chip),金線(Gold Wire),銀膠(Silver Epoxy),晶片座(Die Pad),引腳(Lead),BGA(Ball Grid Array)構造,缺點：膠體不對稱，易產生翹曲,First bonding,Mold compound,Chip,Go

4、ld wire,Ag paste,Through hole,Ball mount 目的： 接地&散熱,Thermal via hole,Ground,Solder pattern,Solder balls,Solder resist,Bonding pattern,Second bonding,使用導線架(Leadframe)之單晶片構裝,1. L型引腳 (Lead),2. J型引腳,3. I型引腳,4. 無引腳 (Non Lead) QFN(Quad Flat Non-lead),5. 晶片座 (Die Pad),優點：1. 散熱能力佳 2. 面積小(無須預留接腳空間) 3. 傳輸距離短 4

5、. 無腳彎翹風險 缺點：Molding 困難度較高 (不對稱，易發生翹曲 ),優點：散熱能力佳,晶片互連技術(Chip Interconnection),1. 焊線接合(Wire Bonding)使用金線或鋁線， 以熱壓及超音波接合,2. 覆晶接合(Flip Chip Bonding)使用錫鉛迴銲或(非)導電膠固化接合,3. 卷帶式接合(TABTape Automatic Bonding)使用金對金熱壓接合,Solder ball bond 不用打線,Gold bond,註： TCP ( Tape Carrier Package ) 應用在LCD driver上。,單晶片構裝之演變,PTH S

6、MT Area Array Fine Pitch Area Array,1970 1980 1990 2000 2010,TO,DIP,QFP,PGA,BGA,TCP,Chip Scale Package,Direct Chip Attach on Board,* 一定要使用較小的IC (CTE過大易裂 ),Wire Bond Flip Chip 的應用 1.電訊上的考慮(速度、 傳輸路徑短 ) 2. IO數的考量(IO數較Ball Pad受限),BGA構裝之分類,Plastic Tape Ceramic,CSP(Chip Scale Package), Definition： Chip sc

7、ale package (CSP) is a package whose package-to-silicon area ratio less than 120 percent. CSP is derived from existing packages, that is, it can be any type of packages.,Silicon,Chip Scale 構裝,覆晶(Flip Chip)技術 小尺寸 低電感 高I / O,表面黏著技術(Surface Mount) 標準化 易於生產 可測性 可重工 可靠性,定義：,Package area,Silicon area, 1.2

8、,說明：封裝體愈小愈好， CSP並非是封裝的名稱， 只是封裝中的一類； 不同於PBGA,CSP之分類,硬板中介層(Rigid Substrate Interposer) 導線架形式(Leadframe Type) 軟板中介層(Flex circuit Interposer) 無中介層， 壓模成型(Transfer Molding) 晶圓層級(Wafer-Level),說明：先電鍍再上球， Sawing完後再封裝,PI 聚亞矽氨,說明：所有封裝在Wafer完成後， 再Sawing,3D Packages,Wire Bonding,Wireless Bonding ( FCB , others )

9、,COC (Chip on Chip),CIB (Chip in Board),Through Hole,疊Die後再鑽孔； 目前市場上尚無此類產品。,Multi Chip Module (MCM), Definition： Multi chip module is module or package which usually contains a high density interconnect substrate, several active and passive components, and a package which can be connected to the nex

10、t level of interconnection.,Chip,Single Chip Module,Chip,Chip,Chip,Chip,Multi Chip Module,What is KGD?, Known Good Die (KGD) is a which has been manufactured and delivered in a bare, or minimally packaged die format, which has quality and reliability comparable to its functionally equivalent package

11、d component, can be interconnected to its next level of packaging by wire bond, tape automated bonding, or flip-chip. 說明： 已知是好的Die封裝進度， Wafer sawing 無法100% 檢出IC是好是壞? 原因： 檢驗困難度高 成本貴 大部份的是IC封完後測出IC是好是壞?,封裝製程介紹 IC Assembly Process Introduction,PBGA Assembly Process,Wafer Incoming,Wafer Grinding,Wafer S

12、awing,Die Bonding,Plasma Clean,Wire Bonding Interconnecting 完成,Molding,Ball Mount,Reflow,Flux Clean,Singulation (Punch or Routing),Ball Scan,Final Inspection,Taping,De-Taping,Substrate pre-bake,Curing,O/S Test or 3rd Vision Insp.,Plasma Clean,Top Marking & Curing,Assembly Process,Wafer Incoming,Wafe

13、r Incoming Inspection,Wafer in wafer carrier Wafer in wafer box Dice in waffle pack,檢驗方法： 一般都是以抽驗方式執行。 (例如一個Wafer lot 抽 12 wafers, 每個wafer 固定檢驗 pcs 10 pcs ) 檢驗工具： 一般檢驗：光學顯微鏡 30X100X 辨認用：金相高倍顯微鏡 100X1000X,Assembly Process,Wafer Grinding,Wafer in Taping ( Top Side ) - To protect die surface 2. Wafer G

14、rinding ( Bottom Side ) - To get needed die thickness Wafer Cleaning / Drying De-Taping - To remove taping tape,Assembly Process,Wafer Mount,Wafer Mounting ( Bottom Side ) - To put wafer onto tape & wafer frame - Blue tape or UV tape 說明： Blue tape 黏性一致 UV tape 黏性較 Blue tape強， 照 UV光後黏性會降低， 較易取 Die；缺點

15、是成本較貴 Control Item： No bubble & particle on the backside No Wafer crack, chipout or scratch,Assembly Process,Wafer Sawing - To singulate die to single unit - 2 steps cutting 說明：一刀切 Wafer 所受應力較大 二刀切割方式缺點是耗時 Water Cleaning / Drying 說明： 純水有規格，因純水不易導電，所以需添加二氧化碳；自來水有一些況物質或雜質會腐蝕 IC UV Irradiating ( option

16、 process ) -To reduce UV tape adhesion strength,Assembly Process,2nd Optical inspection Die damaged? Sawing quality? Die surface contamination?,Assembly Process,Die Bonding - To pick die onto substrate or lead-frame Curing -To cure die attach adhesive,Assembly Process,常見之Die Bonding 缺陷 Die crack ：頂針

17、 issue ，通常在 Die 的背面，不易發現 - force - size Die mis-placement 放歪，不正 Epoxy contamination - reject for any epoxy on die surface - reject for any epoxy on lead Epoxy overflow 注意事項：膠不可高於 Die 面，die bond 有污染與Short風險 5. Epoxy cover 75%,Assembly Process,Wire Bonding Plasma Cleaning ( optional ) - To clean bondi

18、ng pad surface to increase bonding quality Wire Bonding - To bond gold wire to connect die and substrate,Production 檢測項目 Wire pull Ball shear,Assembly Process,Loop High Control 打線高度須受限，Base on compound 高度，一般而言，需保留 Surface距離,25um,10um 以上,常見之Wire Bonding 缺陷 Bond on epoxy / foreign material Missing wir

19、e Bond lift 金線脫落 non stick on pad - NSOP non stick on lead - NSOL Pad metal lift 鋁墊拉起可能原因 (1) 污染 (2) 打線參數不佳,Assembly Process,5. Sagging wire 線塌：人為導致的比率較高 Shorting wire Shorting bond Miss-placed bond 其他( Over bond、 Stray wire),Molding,Plasma Cleaning ( optional ) - To modify substrate surface conditi

20、on to increase adhesion strength between molding compound & substrate. Molding - To protect die & gold wire from damage, easy to handle. Post Mold Curing - To cure molding compound 175 / 8 hrs,Assembly Process,功能 1. 清除表面污染 2. 活化綠漆表面，增加Compound 的附著力,固體EMC移送成型-Transfer Molding,Transfer molding方法 半導體Ch

21、ip / Leadframe 半成品置入成型模具 預熱後固狀封裝材料投入成型機 Pot中 模具溫度約175 條件下，封裝材料溶融，以 Plunger 加壓材料流入模具中 封裝材料加壓成型熱硬化90 120 秒後，模具打開取出成品，完成半導體成型封裝,建議後硬化條件 Post Mold Cure Condition,Molding condition template,轉進時間：取決壓桿速度影響模流,材料成型 成型前準備 Preparation,冷凍保存(10 ) Cold Storage (10 ),回溫Stabilizing ( 25 , 5070%RH ),成型 Molding,再保存(必

22、要時 ) Re-Storage,在成型車間, 原封不動. 需回溫1624小時. (溫度平衡),1. 不要用手直接碰觸黑膠 2. 24小時內使用完畢,1. 需重新包裝好 2. 回溫後24小時內用完,說明：用剩下的,大部份會丟掉(因Compound粒碇在常溫下仍會吸濕與反應 再使用可能會有品質問題),常見之Molding 缺陷 充填不良 ( Incomplete Fill ) 黏膜 ( Sticking ) 氣孔 ( Void/Blister ) 金線歪斜 ( Wire Sweep ) 晶片座偏移 ( Pad Shift ) 表面針孔 ( Rough Surface in Pin Hole) 流痕

23、 ( Flow Mark ) 溢膠 ( Resin Bleed ),金線歪斜 ( Wire Sweep ),PBGA Assembly Process,Ball Mounting,Flux - To print flux onto ball pad area Ball Mounting - To place solder ball onto substrate Reflow - To connect solder ball & substrate Flux Cleaning - To clean residual flux,Assembly Process,Ink Marking 方式 蓋印

24、雷射,PBGA Assembly Process,Singulation Singulation - To singulate package from strip to single unit Ball Scan - To check coplanarity ( PKG warp & ball standoff quality) Final Inspection - To check PKG appearance quality,FVI & Packing,Assembly Process,Defect of ball Mounting - Missing ball,DoFu BGA vs.

25、 PBGA,差異：切割方式不同； DoFu BGA (Sawing) ； PBGA (Punch),DoFu BGA,PBGA,DoFu Ball Grid Array,Plastic Ball Grid Array,Die Attach Material,Function and Composition of Die Attach Material,Functions Mechanical attachment of die to lead frame pad / substrate Heat transfer from die to lead frame / substrate Elect

26、rical contact from the die to the lead frame / substrate,How to Choose a Suitable Die Attach Material,Material selection consideration 1. Good dispensability 黏度 2. Void free 空洞多, 表示含水氣 3. Good thermal conductivity for heat dissipation 散熱 4. High adhesion strength 黏附力 5. Low stress ( stress 太高, 會產生Wa

27、rpage 膠材 ) 6. Low moisture uptake 不吸水 7. Low ionic content 低鹵素, 鹼性分子 8. Cure profile ( fast cure / snap cure ) Cure 愈快, 應力愈大 9. Work life 回溫時間約一天時間, 沒用完 , 即丟棄 10. Low outgassing ( 跑出來的氣體 ,反沾回表面 ) 11. Low resin bleed out 暈開效果,Good thermal conductivity,銀粉結晶結構 - 片狀不規則結晶體 Silver flakes for electrical co

28、nductive die attach material,Silica ( SiO2 )結晶結構 - 球狀結晶體 Spherical Silica for electrical non-conductive die attach material,Factors of Die Attach Material to Reliability Controlled stress ：warpage and modulus Improved adhesion Reduced moisture absorption,Moisture absorption,Stress,Adhesion,Stress 低

29、, Tg低,Tg高 , 吸水性低,與 Tg有連帶關係,Stress Modulus Stress comes from CTE mis-match Lower adhesive modulus, lower stress,Low Ionic Content Presence of Chloride, Potassium, and Sodium ions in conjunction with moisture may affect package reliability. Corrosion of circuitry and wirebond pads may be caused by ion

30、ically impure material. Modern semiconductor grade materials typically have less than 10 ppm chloride.,Defect Mode,Incomplete Fill 1. 與銀膠 quality有關 2. 點膠量不夠 SM Crack 通常發生在PCT之後 ( 121 , 2個大氣壓力下),Wire Bonding Technology,Bonding Sequence,1. 結金球,2. First Bond,3. 凹弧形,4. Second Bond,5. 截斷金線,Thermosonic Bo

31、nding,Heat PBGA加熱溫度 130 150 Lead frame加熱溫度 210 Force Ultrasonic Energy 超音波能量 Time,Bond Wire,Bond Wire Categories,Gold wire Most popular Aluminum wire For wedge bond Copper wire Emerging for Cu pad IC 說明：COB ( Chip on Board ),Au Wire Categories,Standard Package Thickness Standard Low loop High tensil

32、e / long loop strength Thin Packages Low Loop,Au Wire Chemical Composition,Dopants 1. Standard wire Beryllium dopant is used 2. Low loop Beryllium and Ca used by all PPM levels differ for thin PKG 3. High tensile strength Main Palladium 10% strength higher than others. 4. Long Loop wire All supplier

33、 uses different dopant. Dopants are proprietary of suppliers 5. Max content level ：usually Ag 30 ppm, Ca 30 ppm, and Be 10 ppm,Epoxy Molding Compound,Compounds of EMCs Used in Packages,說明: T.C: Thermal Conductivity M.A: Moisture Absorption,Measurement of Compound Properties,Flowability * Spiral Flow

34、 * Kokashiki Viscosity * Laboplasttmill Torque * Cone-Plate Viscometer Filling ability ( Gelled Particle ) * Acetone Insoluble Content Cureability * Gel Time * Curelastmeter Torque * Laboplastmill Stable time * Hot Hardness,Spiral Flow / Flowability,Mold Condition * Sample Powder * Mold Temp. 175 2

35、* Transfer Pressure 70 2 kg / cm2 * Cure Time 120 s * Cull Thickness 3.0 0.3 mm Measurement * Obtain the spiral flow value by measuring the length (cm) of the molded spiral tip.,Gel Time / Cureability,熱盤溫度設定 175 1 將 2g 樣品放置熱盤中 樣品溶融開始計時， 並以刮杓成約 25度角磨動樣品 當硬化時刮杓與樣品剥離， 判定時間即為膠化時間,UL-94 耐燃標準,Vertical Bur

36、ning Test for UL 94 Classification,20 1 mm,Burner,6mm max,300 10 mm,Specimen,10 1 mm,Cotton,放棉花目的 : 看滴垂物是否會引起燃燒,Coefficient of Thermal Expansion熱膨脹係數,Position,Temp.,Slope : 1,Slope : 2,Tg,Sample,Position, 1, 2 : Coefficient of thermal expansion (10-5 1 / ) Tg : Glass transition temp. ( ),Filler,Fill

37、ers are used to control viscosity, improve strength, reducing shrinkage, coefficient of thermal expansion and water absorption.,Advantages Reduced Shrinkage Improved Toughness Improved Abrasion Resistance Reduces Water Absorption Increased Thermal Conductivity Reduced Thermal Expansion Coefficient,D

38、isadvantages Increased Viscosity Machining Difficulties Increased Dielectric Constant Increased Weight,Si O,Crystalline silica 石英 ( 晶體: 片狀 ),Fused silica 玻璃結構 ( 晶體: 圓球 ),Flip Chip Key Technologies,Flip Chip & Bumping Technology,Flip Chip Assembly,Bumping Technology,HDI / Build-up Substrate, Flip Chi

39、p 是一個技術， 不是一個 Package,Technology vs. Package,Flip Chip is an interconnect technology, not a specific package type,FC CSP,FC MLF,FC PBGA,FC LBGA,Super FC,Stacked fcCSP,主要覆晶封裝生產地區優劣比較,Source : 2006.02.13電子時報,Source : 2006.02.13電子時報,全球覆晶基板供需預估,Kyocera, Fujitsu Kinsus,Flip Chip Assembly Technology,Flip

40、Chip Process Steps,1. Incoming Wafer 2. Incoming Substrate Pre-bake 3. Wafer Mount 研磨 4. Saw 5. 2nd Optical Inspect 6. Die Attach * ( Plasma, option for flux jetting ) Fluxing ( or flux jetting ) Placement(對位放置) * Reflow Flux cleaning 續,Flip Chip Process Steps,7. 3rd Optical Inspect Underfill (灌底膠:

41、填充保護Ball Bond ) *Pre-bake *Plasma clean contact angle measurement *Dispense ( 點膠 ) *Cure Back end processing *Ring / Lid attach *Laser marking *Ball mount,FC Die Attach Overview,Pick from Wafer,Die Flip,Pick from Die Flipper,Die Flux,Place,Reflow,Reflow Process,Solder Bump Composition Eutectic Sn /

42、Pb : 63 /37 183 ( 熔點 ) Pb Free Sn / Ag : 96.5 / 3.5 221 Sn / Ag / Cu : 95.5 / 4 / 0.5 217 Hi-Pb Sn / Pb : 5 / 95 or 10 / 90 310 ,Reliability 較好 ( 溫度 ) 抵抗電遷移, IMG 長的比較長 不易熔,0 10 20 30 40 50 60 70 80 90 100,0 10 20 30 40 50 60 70 80 90 100,350 300 250 200 150 100 50 0,Atomic Percent Tin,Weight Percent

43、 Tin 金屬成分比例,Temperature ,327.502,231.9661,18.3,61.9,97.8, Sn,Sn,固液共存,固液共存,Pb,固態共金結構,L,液態,固態鉛的結晶結構,錫的結晶結構,Die Attach to Underfill Process,迴焊後塗佈,助 焊 劑 塗 佈,晶 片 對 位 與 置 放,錫 球 迴 焊,清 洗 助 焊 劑,預 熱 及 填 充 底 膠,底 膠 後 烘 烤 製 程,Plasma Clean Process,Plasma(氬氣+氧氣) 利用電漿清洗的原理， 清除物體表面的污染物， 使填充膠材與基板材料及晶片表面有極佳的接著能力， 此舉可大

44、幅增加信賴性等級。,Wetting Angle Measurement,Substrate,Water droplet,Spec. : chip height ) Incomplete Underfill 填不滿 Underfill Void 底膠孔洞( Pad Size,Electroplated Bump Process,UBM,Template,Ti , Cu,Plate,Sn/Pb,Sn/Pb,Strip,Sn/Pb,Etch,Sn/Pb,Reflow,Stencil Printing vs. Electroplating,Bump,Regular eutectic solder bu

45、mp 1. Melting point = 183 2. Typical reflow peak temp. range = 220 240 3. Collapse after reflow = 25 40% of bump height 4. Alpha count = 3 25 count/cm2 / hr High Pb solder bump 1. 95 Pb / 5 Sn , liquidus Temp. = 313 2. 97 Pb / 3 Sn , liquidus Temp. = 320 3. Typical reflow peak temp. range = 340 350,

46、Bump,Low alpha solder bump 1. Alpha count = 0.02 count/cm2 / hr 2. Ultra low alpha = 0.002 count/cm2 / hr 3. Preferred low alpha option is low alpha PbSn formulations Lead free bump 1. Pure Sn with M.P. of 232 2. Eutectic Sn : Cu (0.8%) with M.P. of 227 3. Eutectic Sn : Ag (3.5%) with M.P. of 221 4. Sn : Ag (3.5%) : Cu (0.7%) with M.P. of 218 ,UBM Quality Check,For reference only: Test velocity = 100 um/sec Tip height = 6 um above the