寄存器和加减乘除程序

1、1、8位寄存器代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY REG ISPORT(clk , RST : IN STD_LOGIC;D: IN STD_LOGIC_VECTOR(7 DOWNTO 0);Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY REG;ARCHITECTURE rt1 OF REG ISBEGINPROCESS(D,clk,RST)BEGINIF RST=1 THEN Q=;ELSIF(clk=1 AND clkEVENT) THENQ );beginprocess(Clk

2、,G,S,QXIN)beginIF G=0 THENY = qxIN(S);ELSif(rising_edge(clk)thenqxIN(S)=X;end if;end process;end Behavioral;仿真波形图如下，请把CLK周期改成自己的学号后仿真。3.加减法电路程序(1) 超前进位模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CQJW ISPORT(G1,G2,G3,G4,P1,P2,P3,P4,ci

3、n: IN STD_LOGIC;C1,C2,C3,C4:OUT STD_LOGIC);END ENTITY CQJW;ARCHITECTURE rt1 OF CQJW ISBEGINC1= (P1 AND CIN ) OR G1;C2= (p2 and p1 and cin) or (P2 AND G1) OR G2;C3= (P3 AND p2 and p1 and cin) or (P3 AND P2 AND G1) OR (P3 AND G2) OR G3;C4= (P4 AND P3 AND p2 and p1 and cin) or (P4 AND P3 AND P2 AND G1)

4、 OR (P4 AND P3 AND G2) OR (P4 AND G3) OR G4;END ARCHITECTURE rt1;（2）GP模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY GP ISPORT(A,B: IN STD_LOGIC;G,P:OUT STD_LOGIC);END ENTITY GP;ARCHITECTURE rt1 OF GP ISBEGING=A AND B;P= A XOR B ;END AR

5、CHITECTURE rt1;（3）一位加法器模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ADD ISPORT(A,B,C: IN STD_LOGIC;F:OUT STD_LOGIC);END ENTITY ADD;ARCHITECTURE rt1 OF ADD ISBEGINF= A XOR B XOR C ;END ARCHITECTURE rt1;（4）四位加法器模块LIBRARY IEEE;USE IEEE.S

6、TD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ADD4 ISPORT(A,B: IN STD_LOGIC_VECTOR(4 DOWNTO 1);CIN: IN STD_LOGIC;COUT: OUT STD_LOGIC;F : OUT STD_LOGIC_VECTOR(4 DOWNTO 1);END ENTITY ADD4;ARCHITECTURE rt1 OF ADD4 ISCOMPONENT ADDPORT(A,B,C: IN STD_LOGIC;F:OUT STD

7、_LOGIC);END COMPONENT;COMPONENT GPPORT(A,B: IN STD_LOGIC;G,P: OUT STD_LOGIC);END COMPONENT;COMPONENT CQJWPORT(G1,G2,G3,G4,P1,P2,P3,P4,CIN: IN STD_LOGIC;C1,C2,C3,C4:OUT STD_LOGIC);END COMPONENT;SIGNAL C1,C2,C3,C4:STD_LOGIC;SIGNAL G1,G2,G3,G4:STD_LOGIC;SIGNAL P1,P2,P3,P4:STD_LOGIC;BEGINU1:GP PORT map

8、(A(1),b(1),G1,P1);U2:GP PORT map (A(2),b(2),G2,P2);U3:GP PORT map (A(3),b(3),G3,P3);U4:GP PORT map (A(4),b(4),G4,P4);U5:CQJW PORT map (G1,G2,G3,G4,P1,P2,P3,P4,CIN,C1,C2,C3,C4);U6:ADD PORT map (A(1),b(1),CIN,f(1);U7:ADD PORT map (A(2),b(2),c1,f(2);U8:ADD PORT map (A(3),b(3),c2,f(3);U9:ADD PORT map (A

9、(4),b(4),c3,f(4);COUT=C4;END ARCHITECTURE rt1;（5）四异或模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY M4xor ISPORT(A: IN STD_LOGIC_VECTOR(4 DOWNTO 1);M: IN STD_LOGIC;B: OUT STD_LOGIC_VECTOR(4 DOWNTO 1);END ENTITY M4xor;ARCHITECTURE rt1 OF

10、M4xor ISBEGINB(1)=A(1) XOR M;B(2)=A(2) XOR M;B(3)=A(3) XOR M;B(4)=A(4) XOR M;END ARCHITECTURE rt1;（6）溢出判断模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ADD ISPORT(A,B,C: IN STD_LOGIC;F:OUT STD_LOGIC);END ENTITY ADD;ARCHITECTURE rt1 OF A

11、DD ISBEGINF= A XOR B XOR C ;END ARCHITECTURE rt1;（7）加减运算器主程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY addsub ISPORT(A,B: IN STD_LOGIC_VECTOR(4 DOWNTO 1);M : IN STD_LOGIC;yc : OUT STD_LOGIC;y: OUT STD_LOGIC_VECTOR(4 DOWNTO 1);END ENTI

12、TY addsub;ARCHITECTURE rt1 OF addsub ISCOMPONENT ADD4PORT(A,B: IN STD_LOGIC_VECTOR(4 DOWNTO 1);CIN: IN STD_LOGIC;COUT: OUT STD_LOGIC;F : OUT STD_LOGIC_VECTOR(4 DOWNTO 1);END COMPONENT;COMPONENT M4XORPORT( A: IN STD_LOGIC_VECTOR(4 DOWNTO 1);M: IN STD_LOGIC;B: OUT STD_LOGIC_VECTOR(4 DOWNTO 1);END COMP

13、ONENT;COMPONENT ycpdPORT( a,b,c: IN STD_LOGIC;y: OUT STD_LOGIC);END COMPONENT;SIGNAL X,TY:STD_LOGIC_VECTOR(4 DOWNTO 1);SIGNAL COUT:STD_LOGIC;BEGINU1:M4XOR PORT map (B,M,X);U2:add4 PORT map (A,X,M,cout,Ty);u3:ycpd port map (a(4),x(4),TY(4),YC);Y = TY;END ARCHITECTURE rt1;4.乘法电路程序LIBRARY IEEE;USE IEEE

14、.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_arith.ALL;USE IEEE.STD_LOGIC_unsigned.ALL;ENTITY mult ISPORT(B,A: IN STD_LOGIC_VECTOR(4 DOWNTO 1);y: out STD_LOGIC_VECTOR(8 DOWNTO 1);END ENTITY mult;ARCHITECTURE rt1 OF mult ISsignal ta: STD_LOGIC_VECTOR(8 DOWNTO 1) ;BEGINta = 0000 & a;Process(a,b,ta)variable

15、ty :STD_LOGIC_VECTOR(8 DOWNTO 1) ;beginty:=;for i in 1 to 4 loopif b(i) = 1 thenty := ty + to_stdlogicvector(to_bitvector(ta) sll (i - 1);- SLL 左移 左操作数必须是BIT_VECTOR，右操作数必须是INTEGER-先把 TA转换为BIT_VECTOR，移位后再转换成stdlogicvector-ta 移位后的值与TY相加，ta保持不变end if;end loop;y= ty;end process;END ARCHITECTURE rt1;5.除法电路程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY div4 ISgeneric(n:integer:=3);PORT(A,B: IN integer range 0 to 15;err:OUT STD_LOGIC;y: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);rest:OUT integer range 0 to