数字电路自由创作(二)

1、数电实验报告题 目 基于FPGA的洗衣机控制系统的实现 时 间 2011年6月27日 摘要 本试验基于FPGA设计了简单的洗衣机控制系统，该系统能实现包括定时，洗衣等功能。本试验主要利用VHDL语言写出相关的程序，然后通过仿真软件modelsim进行模拟仿真。关键词洗衣机 控制系统 FPGA目录第一章 实验任务与原理 2第二章 FPGA模块程序设计与仿真 2附录 22第一章 实验任务与原理1、 功能需求（1）设计一个洗衣机控制器，使洗衣机作如下运转：定时启动正转20秒暂停10秒反转20秒暂停10秒定时不到，重复上面过程；（2）若定时到，则停止；（3）用两个数码管显示洗涤的预置时间（分钟数），按

2、倒计时方式对洗涤过程作计时显示，直到时间到停机；洗涤过程由开始信号开始；（4）三只LED灯表示正转、反转、暂停三个状态。2、原理阐述洗衣机控制器的设计主要是定时器的设计，由一片FPGA和外围电路构成了电器控制部分。FPGA接收键盘的控制命令，控制洗衣机的进水、排水、水位和洗衣机的工作状态、并控制显示工作状态以及设定直流电机速度、正反转控制、制动控制、起停控制和运动状态控制。对FPGA芯片的编程采用模块化的VHDL (硬件描述语言)进行设计。定时启动正转反转暂停暂停停止定时未到定时到 图一 洗涤过程第二章 FPGA模块程序设计与仿真洗衣机控制器电路主要有五大部分组成，包括：减法计数器、时序控制电

3、路、预置时间和编码电路、数码管显示、译码器组成。 图二 洗衣机控制器电路说明图1、预置时间和编码电路（1）、模块源程序 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents

4、.all;entity test_2 is port(clk:in std_logic; reset:in std_logic;set:in std_logic; load:in std_logic_vector(9 downto 0);en_out:out std_logic_vector(3 downto 2);dout_p:out std_logic_vector(7 downto 0);end test_2;architecture Behavioral of test_2 is signal p1:std_logic_vector(7 downto 0);beginprocess(c

5、lk,load,reset,set) begin if(reset=1) then p1p1p1p1p1p1p1p1p1p1p1p1=; end case; if(p1=) then en_out(3)=1; en_out(2)=0; dout_p=; else en_out(3)=0; en_out(2)dout_pdout_pdout_pdout_pdout_pdout_pdout_pdout_pdout_pdout_p 0); -Outputs signal en_out : std_logic_vector(3 downto 2); signal dout_p : std_logic_

6、vector(7 downto 0); - Clock period definitions constant clk_period : time := 10 ns; BEGIN - Instantiate the Unit Under Test (UUT) uut: test_2 PORT MAP ( clk = clk, reset = reset, set = set, load = load, en_out = en_out, dout_p = dout_p ); - Clock process definitions clk_process :process beginclk = 0

7、;wait for clk_period/2;clk = 1;wait for clk_period/2; end process; - Stimulus process stim_proc: process begin - hold reset state for 100 ns. reset=1;set=0;wait for 50 ns; reset=0; set=1; load=; wait; end process;END;（3）、模拟结果图 2、定时器模块（1）、模块源程序 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_lo

8、gic_arith.all;use ieee.std_logic_unsigned.all;entity test_1 is port(clk:in std_logic; reset:in std_logic;start:in std_logic;p1:in std_logic_vector(7 downto 0);time_is_up_out:out std_logic;count_out:out std_logic_vector(19 downto 0);en_out:out std_logic_vector(1 downto 0);dout_p:out std_logic_vector(

9、7 downto 0);end test_1;architecture Behavioral of test_1 is signal time_remain: std_logic_vector(7 downto 0);signal time_is_up:std_logic;signal count:std_logic_vector(19 downto 0);beginprocess(clk,reset,start,p1) -variable time_temp:int; begin if(reset=1) then time_remain=p1;time_is_up=0;count=; els

10、if(clkevent and clk=1) then if(start=1 and time_is_up=0) then if(time_remain=) then time_is_up=1; else if(count=) then count=; time_remain=time_remain-1; else count=count+1; end if;end if;count_out=count;time_is_up_out=time_is_up; if(time_remain=) then en_out(1)=1; en_out(0)=0; dout_p=; else en_out(

11、1)=0; en_out(0)dout_pdout_pdout_pdout_pdout_pdout_pdout_pdout_pdout_pdout_p=; end case; end if;end if;end if;time_is_up_out 0); -Outputs signal time_is_up_out : std_logic; signal count_out : std_logic_vector(19 downto 0); signal en_out : std_logic_vector(1 downto 0); signal dout_p : std_logic_vector

12、(7 downto 0); - Clock period definitions constant clk_period : time := 10 ns;BEGIN- Instantiate the Unit Under Test (UUT) uut: test_1 PORT MAP ( clk = clk, reset = reset, start = start, p1 = p1, time_is_up_out = time_is_up_out, count_out = count_out, en_out = en_out, dout_p = dout_p ); - Clock proce

13、ss definitions clk_process :process beginclk = 0;wait for clk_period/2;clk = 1;wait for clk_period/2; end process; - Stimulus process stim_proc: process begin - hold reset state for 100 ns. reset=1;start=0;p1=;wait for 10 ns; reset=0;start=1; wait; end process;END;（3）、仿真结果图3、洗衣控制模块（1）、模块源程序 library

14、IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;entity test_3 is port(clk:in std_logic; reset

15、:in std_logic; start:in std_logic; time_is_up:in std_logic; rev,run,pause:out std_logic );end test_3;architecture Behavioral of test_3 is signal cnt:std_logic_vector(18 downto 0);signal q1,q2:std_logic;beginprocess(clk,reset,start,time_is_up)begin if(reset=1) then q1=0; q2=0; pause=0;cnt=; elsif(clk

16、event and clk=1)then if(start=1 and time_is_up=0) then if(cnt=) then cnt=; q1=1; q2=0; pause=0; elsif(cnt=) then q1=0;q2=0;pause=1; elsif(cnt=) then q1=0;q2=1;pause=0; elsif(cnt=) then q1=0;q2=0;pause=1; end if; cnt=cnt+1;end if;end if;run=q1; rev clk, reset = reset, start = start, time_is_up = time

17、_is_up, rev = rev, run = run, pause = pause ); - Clock process definitions clk_process :process beginclk = 0;wait for clk_period/2;clk = 1;wait for clk_period/2; end process; - Stimulus process stim_proc: process begin - hold reset state for 100 ns. reset=1;start=0;time_is_up=0;wait for 10 ns; reset

18、=0;start=1;time_is_up=0; wait; end process;END;（3）、仿真结果图附录：本试验的源程序library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL

19、;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity xiyi is port( clk:in std_logic;reset:in std_logic;start:in std_logic; set:in std_logic;load:in std_logic_vector(9 downto 0);en_out:out std_logic_vect

20、or(3 downto 0);time_is_up_out:out std_logic;rev:out std_logic;run:out std_logic;pause:out std_logic;dout_p_T,dout_p_s:out std_logic_vector(7 downto 0);time_left_out: out std_logic_vector(7 downto 0);count_out:out std_logic_vector(19 downto 0);p1_out:out std_logic_vector(7 downto 0);end xiyi;architec

21、ture Behavioral of xiyi is signal q1,q2:std_logic; signal time_is_up:std_logic; signal pause_z,pause_f:std_logic; signal p1:std_logic_vector(7 downto 0); signal time_left:std_logic_vector(7 downto 0); signal count:std_logic_vector(19 downto 0); signal cnt:std_logic_vector(18 downto 0);begin-定时器电路-pr

22、ocess(clk,reset,start,set) begin if(reset=1) thentime_is_up=0;count=; elsif(clkevent and clk=1 and set=0) then if(start=1 and time_is_up=0) then if(time_left=) then time_is_up=1; else if(count=) then count=; time_left=time_left-1; else count=count+1; end if;end if; if(time_left=) then en_out(1)=1; en_out(0)=0; dout_p_T=; else en_out(1)=0; en_out(0)dout_p_Tdout_p_Tdout_p_Tdout_p_Tdout_p_Tdout_p_Tdout_p_Tdout_p_Tdout_p_Tdout_p_T=; end case; end if;end if;end if;time_is_up_out=time_is_up;time