英语翻译任务-H3.5段.ppt

1、H.3.5 Built-in Self-Test (BIST),什么是BIST测试技术？ Built-in Self Test 简称BIST是在设计时在电路中植入相关功能电路用于提供自我测试功能的技术，以此降低器件测试对自动测试设备（ATE）的依赖程度。 它是一种DFT（Design for Testability/可测性设计）技术，它可以应用于几乎所有电路，因此在半导体工业被广泛应用。举例来说，在DRAM中普遍使用的BIST技术包括在电路中植入测试图形发生电路，时序电路，模式选择电路和调试测试电路。 BIST技术的快速发展很大的原因是由于居高不下的ATE成本和电路的高复杂度。现在，高度集成的

2、电路被广泛应用，测试这些电路需要高速的混合信号测试设备。BIST技术可以通过实现自我测试从而减少对ATE的需求。BIST技术也可以解决很多电路无法直接测试的问题，因为他们没有直接的外部引脚，比如嵌闪。可以预见，在不久的将来即使最先进的ATE也无法完全测试最快的电路，这也是采用BIST的原因之一。,内建自测,An alternative and attractive approach to testability is having the circuit itself generate the test Patterns instead of requiring the application

3、 of external patterns Wang86. 可测性的一个替代性和吸引力的方法是电路本身产生的，而不需要对应用Wang86外部模式的测试模式。,一,Even more appealing is a technique where the circuit itself decides if the obtained results are correct. 更吸引人的是一种技术，电路本身的决定，如果得到的结果是正确的。,一,一,Depending upon the nature of the circuit, this might require the addition of e

4、xtra circuitry for the generation and analysis of the patterns. 根据电路的性质，这可能需要增加额外的电路模式的产生和分析。,Some of this hardware might already be available as part of the normal operation, and the size overhead of the self-test can be small. 某些硬件可能已可正常运作的一部分，自检的大小开销小。,一,The general format of a built-in self-test

5、 design is illustrated in Figure H-10 (Kornegay92).It contains a means for supplying test patterns to the device under test and a means of comparing the devices response to a known correct sequence. 在一般格式的1个内置的自检设计是在图所示H-10（Kornegay92）。它包含1种提供测试的测试模式设备的手段和比较设备的响应的已知的正确的手段序列。,二,激励电机,响应分析仪,检测电路,通常的内置自

6、测方式结构图,检测控制,There are many ways to generate stimuli. 有许多方法来产生刺激。 Most widely used are the exhaustive and the random approaches. 使用最广泛的全面的和随机方法。 In the exhaustive approach, the test length is , where N is the number of inputs to the circuit. 在全面的方法，测试长度为 ，其中N是数字电路的输入。,三,The exhaustive nature of the t

7、est means that all detectable faults will be detected, given the space of the available input signals. 全面的测试性质意味着所有检测到的故障将被检测到，由于可用的输入信号的空间。,三,An N-bit counter is a good example of an exhaustive pattern generator .For circuits with large values of N, the time to cycle through the complete input spac

8、e might be prohibitive. N位计数器是一个详尽的模式发生器的一个很好的例子。对于电路的N大值，周期时间，通过完整的输入空间可能望而却步。,三,An alternative approach is to use random testing that implies the application of a randomly chosen sub-set of possible input patterns. 另一种方法是使用随机测试，这意味着2个随机选择的子集 n个 可能的输入模式的应用。,三,This subset should be selected so that

9、a reasonable fault coverage is obtained. 应选择该子集，因此，得到一个合理的故障覆盖率。,三,三,An example of a pseudorandom pattern generator is the linear-feedback shift register (or LFSR), which is shown in Figure H-11. 一个例子是一个伪随机码型发生器的线性反馈移位寄存器（LFSR的），这是在图H-11所示。,It consists of a serial connection of 1-bit registers. 它由一个

10、1位寄存器的串行连接。,注：线性反馈移位寄存器(LFSR)是一个产生二进制位序列的机制。,3位线性反馈移位寄存器 和其产生的序列,Some of the outputs are XORd and fed back to the input of the shift register, An N-bit LFSR cycles through 1 states before repeating the sequence, which produces a seemingly random pattern. 输出一些XORd (XOR:异或)和反馈移位寄存器的输入，重复序列前N位LFSR通过 -1

11、状态周期，从而产生一种看似随意的模式 。,三,Initialization of the registers to a given seed value (different from 0 for our example circuit) determines what will be generated, subsequently. 初始化寄存器到一个给定的种子值（0）在我们的例子电路决定会产生什么，其次。,三,The response analyzer could be implemented as a comparison between the generated response a

12、nd the expected response stored in an on-chip memory, but this approach represents too much area overhead to be practical. 响应分析仪可以作为生成的响应和预期响应存储在片上存储器之间的比较，但这种做法表示实际面积开销太大。 A cheaper technique is to compress the responses before comparing them. 一个便宜的方法是压缩前比较，他们的反应。,四,Storing the compressed response

13、of the correct circuit requires only a minimal amount of memory, especially when the compression ratio is high. 存储压缩的响应，正确的电路只需要少量的内存，尤其是当压缩比是很高的。 The response analyzer then consists of circuitry that dynamically compresses the output of the circuit under test and a comparator. 响应分析仪，然后由电路，动态压缩下测试和比

14、较电路输出。,四,The compressed output is often called the signature of the circuit, and the overall approach is dubbed signature analysis. 通常被称为压缩输出电路的标记，和整体的方法被称为特征分析。,四,An example of a signature analyzer that compresses a single bit stream is shown in Figure H-12. 签名分析仪，压缩单一的比特流的例子在图H-12所示。,五,单位流特征分析,五,I

15、nspection reveals that this circuit simply counts the number of 0 1 and 1 0 transitions in the input stream. 检查结果显示，该电路简单的计数输入流中的01和10的跳变。,This compression does not guarantee that the received sequence is the correc t one; that is, there are many different sequences with the same number of transitio

16、ns. 这种压缩并不保证接收到的序列是一个校正;是，有许多不同的序列，与相 同数量的转换。 Since the chances of this happening are slim, it may be a risk worth taking if kept within bounds. 由于这种情况发生的机会很渺茫，它可能是一个值得考虑，如果保持在一定范围内的风险。,五,Another technique is illustrated in Figure H-13a. 另一种方法是在图H-13A所示。,六,3位BILBO寄存器,六,It represents a modification o

17、f the linear-feedback shift register and has the advantage that the same hardware can be used for both pattern generation and signature analysis. 它代表了一种线性反馈移位寄存器的修改，并具有相同的硬件，可以使用两种模式的产生和特征分析的优势。,Each incoming data word is successively XORd with the contents of the LFSR. 先后与LFSR的内容XORd每个传入的数据字。 At th

18、e end of the test sequence the LFSR contains the signature, or syndrome, of the data sequence, which can be compared with the syndrome of the correct circuit. 在测试序列的LFSR包含签名，或综合征，数据序列，可以比较正确的电路综合征。,六,六,The circuit not only implements a random-pattern generator and signature analyzer , but also can b

19、e used as a normal register and scan register , depending on the values of the control signals B0 and B1(Figure H-13b) . 这个电路不仅实现了随机码发生器和特征分析器,而且还可以作为通用寄存器和扫描寄存器,这要根据控制信号B0 和B1的值来确定.,六,BILBO模式,This test approach , which combines all the different techniques , is known as built-in logic block observa

20、tion , or BILBOKoeneman79 , Figure H-13c illustrates the typical use of BILBO.,这种组合了所有不同技术的测试方法就是内建逻辑块观察法(BILBO).图H-13C展示了这种方法的典型应用.,六,BILBO 应用,Using the scan option , the seed is shifted into the BILBO register A while BILBO register B is initialized . 使用扫描选项模式, BILBO寄存器A中的数据被位移的同时寄存器B已经初始化. Next ,

21、registers A and B are operated in the random pattern-generation and signature-analysis modes , respectively . At the end of the test sequence , the signature is read from B using the scan mode . 接下来，寄存器A和B都以随机码生成和特征分析模式被操作，不同的是,在测试序列的最后面，数字特征是从寄存器B中在扫描模式下读取。,六,Finally , it is worth mentioning that s

22、elf-test is extremely beneficial when testing regular structures such as memories . 最后，值得一提的是，这种方法用于测试结构有规律电路是非常有用的,如存储器。 It is not easy to ensure that a memory , which is a sequential circuit , is fault free . 当被测试存储器是有次序的电路时,就不那么容易了.,七,The task is complicated by the fact that the data value read f

23、rom or written into a cell can be influenced by the values stored in the neighboring cells because of cross coupling and other parasitic effects . 事实上,因交叉耦合和其他寄生效应的作用,写入或读出一个单元的数据受到相邻单元存储数据的影响,因此,这个问题就变得比较复杂了.,七,Memory tests , therefore , include the reading and writing of a number of different patt

24、erns into and from the memory using alternating addressing sequences . 存储器测试包括用一系列变化寻址的方式从存储器中读取或写入许多不同的码字.,七,Typical patterns can be all zeros or ones , or checkerboards of zeros and ones . 典型的码字可以是全0或全1,或0、1的矩阵. Addressing schemes can include the writing of the complete memory , followed by a comp

25、lete read-out or various alternating read-write sequences . 寻址策略可以是先存储器的全写入,然后全部读出或各种交替读写系列.,七,With a minimal overhead compared with the size of a memory , this test approach can be built into the integrated circuit itself , as illustrated in Figure H-14 .,用最小的测试开销和内存的尺寸相比,这种测试方法可以集成到电路里面,如图H-14所示.,

26、七,内存自检,This approach significantly improves the testing time and minimizes the external control . 这种方法大大提高了测试时间，并最大限度地减少了外部控制。,七,Applying self-test is bound to become more important with the increasing complexity of integrated components and the growing popularity of embedded memories .随着集成部件的复杂成都越来

27、越高和内置存储器的流行,运用自测试方式的重要性势必越来越高.,七,The advent of the systems-on-a-chip era does not make the test job any easier . 随着SOC时代的来临并没有使测试工作更简单容易.,八,注：SOC（系统级芯片）,A single IC may contain micro- and signal processors , multiple embedded memories , ASIC modules , FPGAs and on-chip busses and networks . 单个集成电路可能

28、包括微处理器、信号处理器、多个内置存储器、ASIC模块、FPGA和片上总线和网络等.,ASIC:专用集成电路,FPGA:现场可编程门阵列,八,Each of these modules has its own preferred way of being tested , and combining those into a coherent strategy is quite a challenge . 每个模块都有自己独特的测试方式,如果将他们的测试方案糅合在一起,确实一个不小的困难. Build-in self-test is really the only way out . 内置自检

29、测确实是唯一的出路.,八,A structured test-methodology for systems-on-a-chip , based on BIST is shown in Figure H-15 . 图H-15展示了基于BIST的SOC结构化的测试方法.,八,系统单芯片测试方法,Each of the modules composing the system connects to the on-chip network through a “wrapper .” 组成整个系统的逻辑单元通过一个”外套”连接到片上总线中.,八,This is a customized interf

30、ace between the block and the network , supporting functions such as synchronization and communication . 这个处于逻辑块和网络总线之间的自定义的接口支持诸如同步和通信的功能. This wrapper can be extended to include a test support module . 这个外套也可以扩展到包括支持测试功能.,八,For instance , for an ASIC module that includes a scan chain , the test su

31、pport module provides the interface to the scan chain and a buffer for the test patterns . 比如说,对于一个包括扫描链的专用集成电路,测试支持模块提供一个支持面向扫描链的接口和一个测试码的缓存.,八,This buffer can be directly written and read through the system bus . 且这个缓存可以通过系统总线直接读取.,Similarly , a memory module can be equipped with a pattern generator and signature analysis . 同样的,一个存储模块可以配置测试码发生器和特征分析器.,八,All of this would