IC制造流程简介.ppt

1、IC制造流程简介,基本概念,半导体是指导电能力介于导体和绝缘体之间的材料，其指四价硅中添加三价或五价化学元素而形成的电子元件，它有方向性，可以用来制造逻辑线路使电路具有处理资讯的功能。 半导体的传导率可由搀杂物的浓度来控制：搀杂物的浓度越高，半导体的电阻系数就越低。 P型半导体中的多数载体是电洞。硼是P型的掺杂物。 N型半导体的多数载体是电子。磷，砷，锑是N型的搀杂物。 集成电路（IC) 是指把特定电路所需的各种电子元件及线路缩小并制作在大小仅及2平方公分或更小的面积上的一种电子产品。 集成电路主要种类有两种：逻辑LOGIC及记忆体MEMORY。前者主要执行逻辑的运算如电脑的微处理器后者则如只

2、读器READ ONLY 及随机处理器RANDOM ACCESS MEMORY等。,集成电路(IC)产业主要分为设计生产测试 封装四个阶段. 集成电路的生产主要分三个阶段：,基本概念,基本制程,基本制程,原理：在晶片表面上覆上一層感光材料，來自光源的平行光透過光罩的圖形，使得晶片表面的感光材料進行選擇性的感光。 感光材料：正片經過顯影(Development)，材料所獲得的圖案與光罩上相同稱為正片。負片如果彼此成互補的關係稱負片,微影制程 -1,微影制程 -2,掺杂物(Doping)概念: To get the extrinsic semiconductor by adding donors o

3、r acceptors, which may cause the impurity energy level. The action that adding particular impurities into the semiconductor is called “doping” and the impurity that added is called the “dopant”.,Doping介绍,Doping 方法: 1. 扩散（Diffusion） 2. 离子植入（Implantation）,Pre-deposition: 将掺杂物置于wafer表面. Generally used

4、dopant resource furnace design:,Carrier gas,Heater,石英管,Solid dopant source furnace,O2,Liquid dopant source,Carrier gas,Gas dopant source,Valve,O2,(a),(c),(b),扩散制程（DIFF) -1,Solid dopant source,Drive-in: To implant the dopant into the wafer by the thermal process,扩散制程（DIFF) -2,1. The definition: A man

5、ufacturing process that can uniformly implants the ions into the wafer in the specified depth and consistence by selecting and accelerating ions. 2. The purpose: To change the resistance value of the semiconductor by implanting the dopant. 3. Energy range (8 years ago) (1) General process：10 KeV - 1

6、80 KeV (0.35m) (100KeV for 0.18 m now) (2) Advanced process：10 KeV - 3 MeV (0.5m) (3) R&D process：0.2 KeV - 5 KeV,离子植入制程(IMP) -1,Dopant Source,Ion Source,Mass Analysis,Accelerator,Scanner,Electron Shower,Extractor,Farady Cap,离子植入制程(IMP) -2,Parameters Doping elementsselection Scanning uniformity cont

7、rol Temperature control Concentration control,Factors The selection of the ion resource The design of the mass analyzer Scanning system Vacuum control Precise wafer position control Preciseand stable electric power supplier The measurement of the ion current (Farady Cup),DOPING参数,DC,Metal Target,Gas

8、 In,To The Vacuum Pump,Wafer,Plate,Collimator,PVD制程,(a) Reagents diffuse through the interface boundary layer (b) Adsorbed onto the wafer surface (c) Deposition reaction happens (d) Byproducts diffuse through the interface boundary layer (e) Reagents & byproducts pass away,Heat Source,(a) (d) (b) (c

9、),(e),Reaction,Main Stream Interface Boundary Layer Wafer surface,Vacuum System,CVD制程,(1) Thermal Oxidation The growth temperature is above 900 0C. High quality SiO2. (2) Low Pressure CVD (LPCVD) The growth temperature is around 400 0C to 750 0C. Better step coverage ability. (3) Plasma Enhanced CVD

10、 (PECVD) The growth temperature is under 400 0C. In the case of the Al deposition and non-thermal process.,Solutions to Deposition,Down Force,wafer,Wafer Carrier,Carrier Film,Slurry,Carrier,Wafer,Interconnects,Composite Pad,Table,Polishing Pad,Polishing table,p,CMP System Schematic,Carrier Film,c,Ma

11、jor Parameters In CMP,SiO2 CMP: Down Force Rotating Speed (p) Type of The Pad Metal and Si CMP: pH Measurement,* The lower the force-speed ratio the better the planarity,Slurry,Particle (0.1 2.0 um) Silica (Colloidal) Alumina (Dispersed) Liquor (Contains some oxidant and organic reagents in the case

12、 of metal CMP) KOH NH4OH,Wafer Cleaning,Purpose: To remove the remainsand impuriti杂质,Methods: Brush Cleaning Spray Cleaning Ultrasonic 超声波Cleaning,Photo resist,SiO2,Si Substrate,PhotoMask,Positive积极 Resist,Negative负值 Resist,Etching Intro - 1,Next Page,Positive Resist,Negative Resist,Etching Intro -

13、2,Continue,Etching Methods,Wet Etching (Isotropic) Relatively simple process High throughput Low quality Dry Etching (Anisotropic) High quality (due to the excellent pattern transfer ability) Worse selectivity,Wet Etching,Substrate,Thin Film,Solution,Boundary Layer,Reagent,Resultant,Reaction,Photo R

14、esist,(a) Isotropic Etching：A=0 (Erh=Erv),(b) Anisotropic Etching：A=1 (Erh=0),Isotropic & Anisotropic,Isotropic,Quartz dome,Silicon wafer,Silicon carbide coated graphite,RF Coil,Gas in,Gas exit,Silicon carbide susceptor,Gas exit,Silicon wafers,RF induction heating coil,Dry Etching System - 1,(a) Spu

15、ttering Etching,(b) Plasma Etching,(c) Reactive Ion Etching,Ion,Reactive Ion,Volatile Product,Volatile Product,Reactive Ion,RIE,Scheme Diagram of RIE System,Gas In,To Vacuum Pump,Plasma,Electrode,RF,Annealing,SiO2 Post Ion Implantation Annealing,RTP RAPID THERMAL PROCESS 快速升温过程,Furnace,Reaction Room,Gas in (H2),Wafer,3-Zone Heating Element,Gas out,Gas in (O2),Loading Area,Rapid Thermal Processin