ESD Protection Design Seminar.ppt

1、ESD Protection Design Seminar Jim SutherlandSenior Applications Engineer,Outline,What is ESD? What damage can it cause? Why is the problem growing? What are the issues for the designer? How can we measure it? How can we protect equipment from ESD?,What Is ESD?,ESD = Electro Static Discharge Generati

2、on Triboelectric (friction causes accumulation of charge) Induction (field induces charge) Discharge Dielectric (air) breakdown Electric field increases when charged bodies approach each other Current flow into circuitry,ESD Damage of ICs,Permanent Oxide breakdown, shorts, opens, latch-up Temporary

3、Latch-up, ground bounce Latent Degradation from an ESD event,ESD problem is growing,Circuits/Systems Old - Robust ICs many components; large board area Spark gap Low cost; low stability; large board area Discrete Zener diodes High capacitance, many components; large board area Discrete PN diodes Low

4、 capacitance; many components; large board area Integrated PN diodes,Integrated Diode Networks,Superior downstream ESD protection High speed response ESD current steered to GND or VCC Minimum Signal Degradation (Low C) Minimal board space, weight Low assembly/manufacturing costs Minimal Design-In Ti

5、me Long-term reliability,Choosing an ESD Diode Network,How many lines are needed? How much capacitance? (e.g. 5 pF) What is the HBM rating? (e.g. 15 kV) What is the downstream clamp voltage? (e.g. 13 V 15 kV HBM pulse) What is the contact discharge rating? (e.g. 8 kV) What is the air discharge ratin

6、g? (e.g. 15 kV) What package? (e.g. 24-pin QSOP),ESD Diode Network Placement,The Need to Keep ESD Diodes,Downstream of Line Inductances,Also put protection diodes at most likely ESD entry point - the connector,Designing for Minimal PowerRail Inductance,Add Bypass Capacitor,Place Ceramic bypass capac

7、itor (0.1 0.2 uF) as close as possible to ESD diode network power rail to shunt ESD current to both power rails Maybe add Zener in parallel with capacitor to minimize parasitic inductance of bypass capacitor,Protected,Device,Gnd,Vcc,C,Using a Series Resistor toMinimize Downstream Current,Can be cons

8、idered for latch-up sensitive applications Guaranteed clamping voltage limits current downstream (I = V / R) Only for inputs with high Z Only for output drivers with low Z watch out for filtering of signal,Power-down Issues,Diode protected systems that are powered down can drain current from an acti

9、ve high input through the diode to VCC This can drain batteries and/or damage devices on the same line To avoid this, isolate VCC from the bypass capacitor with a blocking diode One diode solution,Component and System Specifications,There is no simple formula to translate system specifications into

10、component specifications IEC 1000-4-2 Specification is more severe than HBM Line capacitance and inductance shape the ESD pulse, reducing its peak value Poor device placement can degrade performance If there are multiple devices on a line, decide which to protect The relationship between downstream

11、clamp voltage and downstream protection is not exact,Validating the Design,Define the practical limits of functional failure (e.g. Data integrity, recovery time) Test only at those places subject to touch during normal operation Use Contact ES Discharges to coupling planes & conductive surfaces, I/O pins, flex pads, and power pins Use Air ES Discharges to insulating surfaces, openings at edges of keys, flex cables, vent areas, seams, slots, apertures,Total Solution Cost,ESD failure is a question of statistics One cannot